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MainMotorDriver/ASM/MainMotorDriver.COD
Executable file
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MainMotorDriver/ASM/MainMotorDriver.COD
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MainMotorDriver/ASM/MainMotorDriver.HEX
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MainMotorDriver/ASM/MainMotorDriver.HEX
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:06010000240893004528CD
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:00000001FF
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MainMotorDriver/ASM/MainMotorDriver.asm
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MainMotorDriver/ASM/MainMotorDriver.asm
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;==========================================================================================================
|
||||
;
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||||
; Wingman MainMotorDriver copyright 2005 v1.0 (2005-04-22)
|
||||
;
|
||||
; Name: Christoffer Martinsson
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||||
; E-mail: cm@wsm.se
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||||
;
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||||
;
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||||
;==========================================================================================================
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include P16F684.INC
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; Temp-registers
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W_TEMP EQU 0x20 ; TempRegister for interrupt-routine
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STATUS_TEMP EQU 0x21 ; TempRegister for interrupt-routine
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DivRegH EQU 0x22 ; TempRegister for div-routine
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DivRegL EQU 0x23 ; TempRegister for div-routine
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SetPWM_Temp EQU 0x24
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; Time-definitions
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minPulseValue =.20000
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maxPulseValue =.40000
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ms1Value =.20000
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ms05Value =.10000
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;==========================================================================================================
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; Reset- and Interrupt-vectors
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;==========================================================================================================
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ORG 0x0000
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GOTO Main ;Reset-vector
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ORG 0x0004
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GOTO Interrupt ;Interrupt-vector
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;==========================================================================================================
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; Macro
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;==========================================================================================================
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;----------------------------------------------------------------------------------------------------------
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; StoreWregInTemp
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;
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; Description: Store Status and working-register in temp-registers
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;
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; Input: -
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; ChangedReg: W_TEMP,STATUS_TEMP
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; UsedReg: W,STATUS,W_TEMP,STATUS_TEMP
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;----------------------------------------------------------------------------------------------------------
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StoreWregInTemp MACRO
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MOVWF W_TEMP ;Copy W to TEMP register
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SWAPF STATUS,W ;Swap status to be saved into W
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CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0
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MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
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ENDM
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;----------------------------------------------------------------------------------------------------------
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; RestoreWregFromTemp
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;
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; Description: Restore Status and working-register from temp-registers
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;
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; Input: -
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; ChangedReg: W,STATUS
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; UsedReg: W,STATUS,W_TEMP,STATUS_TEMP
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;----------------------------------------------------------------------------------------------------------
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RestoreWregFromTemp MACRO
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SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W (sets bank to original state)
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MOVWF STATUS ;Move W into Status register
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SWAPF W_TEMP,F ;Swap W_TEMP
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SWAPF W_TEMP,W ;Swap W_TEMP into W
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ENDM
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;----------------------------------------------------------------------------------------------------------
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; Sub16L
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;
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; Description: Subtract literal from 16bit-register. Reg = Reg - Number, WITH VALID CARRY
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;
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; Input: RegH, RegL, Number
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; ChangedReg: C
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; UsedReg: W
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;----------------------------------------------------------------------------------------------------------
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Sub16L MACRO RegH, RegL, Number
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MOVLW low Number
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SUBWF RegL
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MOVLW high Number
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;BTFSS STATUS,C
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;INCFSZ high Number,W
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SUBWF RegH
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ENDM
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;----------------------------------------------------------------------------------------------------------
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; Set16L
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;
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; Description: Sets 16bit-register to literal. Reg = Number
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;
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; Input: RegH, RegL, Number
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; ChangedReg: C
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; UsedReg: W
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;----------------------------------------------------------------------------------------------------------
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Set16L MACRO RegH, RegL, Number
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MOVLW low Number
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MOVWF RegL
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MOVLW high Number
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MOVWF RegH
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ENDM
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;----------------------------------------------------------------------------------------------------------
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; Clear16
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;
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; Description: Clear 16bit-register.
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;
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; Input: RegH, RegL
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; ChangedReg:
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; UsedReg:
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;----------------------------------------------------------------------------------------------------------
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Clear16 MACRO RegH, RegL
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CLRF RegH
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CLRF RegL
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ENDM
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;----------------------------------------------------------------------------------------------------------
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; Comp16L
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;
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; Description: Compare one 16bit-registers to literal if Reg1=Number then Z=1.
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; if Reg1<Number then C=1.
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; if Number<Reg1 then C=0.
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; Input: RegH, RegL, Number
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; ChangedReg: Z, C
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; UsedReg: W
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;----------------------------------------------------------------------------------------------------------
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Comp16L MACRO RegH, RegL, Number
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MOVF RegH,W
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SUBLW high Number
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BTFSS STATUS,Z
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EXITM
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MOVF RegL,W
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SUBLW low Number
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ENDM
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;----------------------------------------------------------------------------------------------------------
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; SetPWM
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;
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; Description: Sets hardware PWM-output to 8bit register-value. PWM = Reg
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;
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; Input: Reg
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; ChangedReg: CCP1CON(4,5), CCPR1L
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; UsedReg: W, CCP1CON(4,5), CCPR1L, Reg, SetPWM_Temp
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;----------------------------------------------------------------------------------------------------------
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SetPWM MACRO Reg
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BCF STATUS,C
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MOVF Reg,W
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ANDLW b'00000011'
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MOVWF SetPWM_Temp
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RLF SetPWM_Temp,F
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RLF SetPWM_Temp,F
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RLF SetPWM_Temp,F
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RLF SetPWM_Temp,F
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MOVF CCP1CON,W
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ANDLW b'11001111'
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IORWF SetPWM_Temp,W
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MOVWF CCP1CON
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MOVF Reg,W
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ANDLW b'11111100'
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MOVWF SetPWM_Temp
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RRF SetPWM_Temp,F
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RRF SetPWM_Temp,F
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MOVF SetPWM_Temp,W
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MOVWF CCPR1L
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ENDM
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;==========================================================================================================
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; Interrupt routines
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;==========================================================================================================
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Interrupt StoreWregInTemp
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;----------------------------------------------------------------------------------------------------------
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; Timer1_Int
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;
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; Description: Increment pulseIn counter-registers
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;----------------------------------------------------------------------------------------------------------
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Timer1_Int BCF STATUS,RP0 ; Bank 0
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BTFSS PIR1,TMR1IF
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GOTO Int_Return
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BCF PIR1,TMR1IF
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BCF T1CON,TMR1ON ; Timer1 off
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||||
;----------------------------------------------------------------------------------------------------------
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Int_Return RestoreWregFromTemp
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RETFIE
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;==========================================================================================================
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; Sub-routines
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;==========================================================================================================
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;----------------------------------------------------------------------------------------------------------
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; Div16byL
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;
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; Description: Divide a 16bit-register with a literal. DivReg = DivReg / W.
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;
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; Input: DivRegH, DivRegL, W
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; ChangedReg: Z, C, DivRegH, DivRegL
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; UsedReg: W, DivRegH, DivRegL
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||||
;----------------------------------------------------------------------------------------------------------
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Div16byL CALL DivSkipHiShift
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iDivRepeat =8
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WHILE iDivRepeat
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call DivCode
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iDivRepeat--
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ENDW
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RLF DivRegL,F ; C << lo << C
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BCF STATUS,Z
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RETURN ; we are done!
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DivCode RLF DivRegL,F ; C << lo << C
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RLF DivRegH,F ; C << hi << C
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BTFSS STATUS,C ; if Carry
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GOTO DivSkipHiShift
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||||
SUBWF DivRegH,F ; hi-=w
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||||
BSF STATUS,C ; ignore carry
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||||
RETURN ; done
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||||
; endif
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DivSkipHiShift
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SUBWF DivRegH,F ; hi-=w
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||||
BTFSC STATUS,C ; if carry set
|
||||
RETURN ; done
|
||||
ADDWF DivRegH,F ; hi+=w
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||||
BCF STATUS,C ; clear carry
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||||
RETURN
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;==========================================================================================================
|
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; Main
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||||
;==========================================================================================================
|
||||
Main BCF STATUS,RP0 ; Bank 0
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||||
CLRF PORTC ; Clear PORTC
|
||||
CLRF PORTA ; Clear PORTA
|
||||
MOVLW 0x07
|
||||
MOVWF CMCON0 ; Comparator OFF
|
||||
CLRF CCPR1L
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||||
MOVLW b'01001100'
|
||||
MOVWF CCP1CON
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||||
MOVLW b'10000001'
|
||||
MOVWF ADCON0
|
||||
|
||||
BSF STATUS,RP0 ; Bank 1
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||||
MOVLW b'00001101'
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MOVWF TRISA
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||||
CLRF TRISC
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||||
MOVLW b'00000001'
|
||||
MOVWF ANSEL ; All pins to digital I/O except AN0
|
||||
MOVLW 0x3F
|
||||
MOVWF PR2
|
||||
MOVLW b'00100000'
|
||||
MOVWF ADCON1
|
||||
MOVLW b'11001111'
|
||||
MOVWF OPTION_REG
|
||||
|
||||
BCF STATUS,RP0 ; Bank 0
|
||||
BSF T2CON,TMR2ON ; PWM on
|
||||
BSF INTCON,GIE ; Global interrup enable
|
||||
|
||||
; MOVLW low .30000
|
||||
; MOVWF TMR1L
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||||
; MOVLW high .30000
|
||||
; MOVWF TMR1H
|
||||
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; MainLoop
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
Mainloop: BCF STATUS,RP0 ; Bank 0
|
||||
CLRWDT
|
||||
|
||||
;DECODE_PPM
|
||||
PPM_Lo: BTFSC PORTA,2 ; Wait for pulse to go low
|
||||
GOTO PPM_Lo
|
||||
PPM_Hi: BTFSS PORTA,2 ; Wait for pulse to go high (start measuring)
|
||||
GOTO PPM_Hi
|
||||
Clear16 TMR1H,TMR1L ; Clear Timer1 countervalue
|
||||
BSF T1CON,TMR1ON ; Start Timer1
|
||||
PPM_Loop: BTFSC PORTA,2 ; Wait for pulse to go low (stop measuring)
|
||||
GOTO PPM_Loop
|
||||
BCF T1CON,TMR1ON ; Stop Timer1
|
||||
; Comp16L TMR1H,TMR1L,minPulseValue
|
||||
; BTFSC STATUS,C ; If counter < minPulseValue (~1ms)
|
||||
; GOTO Mainloop ; then goto Mainloop
|
||||
; Comp16L TMR1H,TMR1L,maxPulseValue
|
||||
; BTFSS STATUS,C ; else If counter > maxPulseValue (~2ms)
|
||||
; GOTO Mainloop ; then goto Mainloop
|
||||
Sub16L TMR1H,TMR1L,ms1Value ; else counter-value - 1ms
|
||||
Comp16L TMR1H,TMR1L,ms05Value
|
||||
BTFSS STATUS,C ; If counter > 0,5ms
|
||||
GOTO PWM_Fwr ; then goto PWM_forward
|
||||
GOTO PWM_Rev ; else goto PWN_reverse
|
||||
|
||||
PWM_Fwr: BCF CCP1CON,P1M1 ; Set H-bridge in forward-mode
|
||||
Sub16L TMR1H,TMR1L,ms05Value ; counter-value - 0,5ms
|
||||
GOTO PWM_SetVal ; goto PWM_SetValue
|
||||
PWM_Rev: BSF CCP1CON,P1M1 ; Set H-bridge in reverse-mode
|
||||
MOVLW 0xFF
|
||||
XORWF TMR1H,F ; Invert counterH
|
||||
XORWF TMR1L,F ; Invert counterL
|
||||
Sub16L TMR1H,TMR1L,(0xFFFF-ms05Value) ; Inverted counter-value - (65535-0,5ms)
|
||||
|
||||
PWM_SetVal: MOVF TMR1H,W ; Divide by 79...
|
||||
MOVWF DivRegH ; Load div-routine with countervalue
|
||||
MOVF TMR1L,W
|
||||
MOVWF DivRegL ; Load div-routine with countervalue
|
||||
MOVLW ((ms05Value/0xFF)+1) ; Load div-routine with divide-value
|
||||
CALL Div16byL ; Divide!
|
||||
|
||||
SetPWM DivRegL
|
||||
|
||||
GOTO Mainloop
|
||||
END
|
||||
;==========================================================================================================
|
||||
; END
|
||||
;==========================================================================================================
|
||||
255
MainMotorDriver/ASM/MainMotorDriver.asxx
Executable file
255
MainMotorDriver/ASM/MainMotorDriver.asxx
Executable file
@ -0,0 +1,255 @@
|
||||
;==========================================================================================================
|
||||
;
|
||||
; Wingman MainMotorDriver copyright 2005 v1.0 (2005-04-16)
|
||||
;
|
||||
; Name: Christoffer Martinsson
|
||||
; E-mail: cm@wsm.se
|
||||
;
|
||||
;
|
||||
;==========================================================================================================
|
||||
|
||||
include P16F684.INC
|
||||
|
||||
W_TEMP EQU 0x20 ; TempRegister
|
||||
STATUS_TEMP EQU 0x21 ; TempRegister
|
||||
|
||||
PPM_ValueH EQU 0x22
|
||||
PPM_ValueL EQU 0x23
|
||||
|
||||
PulseInH EQU 0x24
|
||||
PulseInL EQU 0x25
|
||||
|
||||
;==========================================================================================================
|
||||
; Reset- and Interrupt-vectors
|
||||
;==========================================================================================================
|
||||
ORG 0x0000
|
||||
GOTO Main ;Reset-vector
|
||||
ORG 0x0004
|
||||
GOTO Interrupt ;Interrupt-vector
|
||||
;==========================================================================================================
|
||||
; Macro
|
||||
;==========================================================================================================
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; StoreWregInTemp
|
||||
;
|
||||
; Description: Store Status and working-register in temp-registers
|
||||
;
|
||||
; Input: -
|
||||
; ChangedReg: -
|
||||
; UsedReg: W,STATUS,W_TEMP,STATUS_TEMP
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
StoreWregInTemp MACRO
|
||||
MOVWF W_TEMP ;Copy W to TEMP register
|
||||
SWAPF STATUS,W ;Swap status to be saved into W
|
||||
CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0
|
||||
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
|
||||
ENDM
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; RestoreWregFromTemp
|
||||
;
|
||||
; Description: Restore Status and working-register from temp-registers
|
||||
;
|
||||
; Input: -
|
||||
; ChangedReg: W,STATUS
|
||||
; UsedReg: W,STATUS,W_TEMP,STATUS_TEMP
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
RestoreWregFromTemp MACRO
|
||||
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W (sets bank to original state)
|
||||
MOVWF STATUS ;Move W into Status register
|
||||
SWAPF W_TEMP,F ;Swap W_TEMP
|
||||
SWAPF W_TEMP,W ;Swap W_TEMP into W
|
||||
ENDM
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Compare16
|
||||
;
|
||||
; Description: Compare two 16bit-registers if Reg1=Reg2 then Z=1.
|
||||
; if Reg1<Reg2 then C=1.
|
||||
; if Reg2<Reg1 then C=0.
|
||||
; Input: Reg1H, Reg1L, Reg2H, Reg2L
|
||||
; ChangedReg: Z, C
|
||||
; UsedReg: W
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
Compare16 MACRO Reg1H, Reg1L, Reg2H, Reg2L
|
||||
MOVF Reg1H,W
|
||||
SUBWF Reg2H,W
|
||||
BTFSS STATUS,Z
|
||||
GOTO Comp16End
|
||||
MOVF Reg1L,W
|
||||
SUBWF Reg2L,W
|
||||
Comp16End ENDM
|
||||
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Sub16
|
||||
;
|
||||
; Description: Subtract 16bit-register. Reg1 = Reg1 - Reg2, WITH VALID CARRY
|
||||
;
|
||||
; Input: Reg1H, Reg1L, Reg2H, Reg2L
|
||||
; ChangedReg: C
|
||||
; UsedReg: W
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
Sub16 MACRO Reg1H, Reg1L, Reg2H, Reg2L
|
||||
MOVF Reg2L,W
|
||||
SUBWF Reg1L
|
||||
MOVF Reg2H,W
|
||||
BTFSS STATUS,C
|
||||
INCFSZ Reg2H,W
|
||||
SUBWF Reg1H
|
||||
ENDM
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Sub16L
|
||||
;
|
||||
; Description: Subtract 16bit-register. Reg1 = Reg1 - Number, WITH VALID CARRY
|
||||
;
|
||||
; Input: Reg1H, Reg1L, Number
|
||||
; ChangedReg: C
|
||||
; UsedReg: W
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
Sub16L MACRO Reg1H, Reg1L, Number
|
||||
MOVF low(Number),W
|
||||
SUBWF Reg1L
|
||||
MOVF high(Number),W
|
||||
BTFSS STATUS,C
|
||||
INCFSZ high(Number),W
|
||||
SUBWF Reg1H
|
||||
ENDM
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Set16L
|
||||
;
|
||||
; Description: Sets 16bit-register to the value of 'Number'. Reg1 = Number
|
||||
;
|
||||
; Input: Reg1H, Reg1L, Number
|
||||
; ChangedReg: C
|
||||
; UsedReg: W
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
Set16L MACRO Reg1H, Reg1L, Number
|
||||
MOVLW low(Number)
|
||||
MOVWF Reg1L
|
||||
MOVLW high(Number)
|
||||
MOVWF Reg1H
|
||||
ENDM
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Clear16
|
||||
;
|
||||
; Description: Clear 16bit-register.
|
||||
;
|
||||
; Input: RegH, RegL
|
||||
; ChangedReg:
|
||||
; UsedReg:
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
Clear16 MACRO RegH, RegL
|
||||
CLRF RegH
|
||||
CLRF RegL
|
||||
ENDM
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Comp16L
|
||||
;
|
||||
; Description: Compare one 16bit-registers to a literal if Reg1=Number then Z=1.
|
||||
; if Reg1<Number then C=1.
|
||||
; if Number<Reg1 then C=0.
|
||||
; Input: Reg1H, Reg1L, Number
|
||||
; ChangedReg: Z, C
|
||||
; UsedReg: W
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
Comp16L MACRO Reg1H, Reg1L, Number
|
||||
MOVF Reg1H,W
|
||||
SUBWF high Number,W
|
||||
BTFSS STATUS,Z
|
||||
EXITM
|
||||
MOVF Reg1L,W
|
||||
SUBWF low Number,W
|
||||
ENDM
|
||||
;==========================================================================================================
|
||||
; Interrupt routines
|
||||
;==========================================================================================================
|
||||
Interrupt StoreWregInTemp
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Timer1_Int
|
||||
;
|
||||
; Description: Increment pulseIn counter-registers
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
Timer1_Int BCF STATUS,RP0 ; Bank 0
|
||||
BTFSS PIR1,TMR1IF
|
||||
GOTO Int_Return
|
||||
BCF PIR1,TMR1IF
|
||||
BCF T1CON,TMR1ON ; Timer1 off
|
||||
|
||||
Int_Return RestoreWregFromTemp
|
||||
RETFIE
|
||||
|
||||
;==========================================================================================================
|
||||
; Main
|
||||
;==========================================================================================================
|
||||
Main BCF STATUS,RP0 ; Bank 0
|
||||
CLRF PORTC ; Clear PORTC
|
||||
CLRF PORTA ; Clear PORTA
|
||||
MOVLW 0x07
|
||||
MOVWF CMCON0 ; Comparator OFF
|
||||
CLRF CCPR1L
|
||||
MOVLW b'01001100'
|
||||
MOVWF CCP1CON
|
||||
MOVLW b'10000001'
|
||||
MOVWF ADCON0
|
||||
; BSF INTCON,INTE
|
||||
|
||||
|
||||
BSF STATUS,RP0 ; Bank 1
|
||||
MOVLW b'00001101'
|
||||
MOVWF TRISA
|
||||
CLRF TRISC
|
||||
MOVLW b'00000001'
|
||||
MOVWF ANSEL ; All pins to digital I/O except AN0
|
||||
MOVLW 0x3F
|
||||
MOVWF PR2
|
||||
MOVLW b'00100000'
|
||||
MOVWF ADCON1
|
||||
MOVLW b'11001111'
|
||||
MOVWF OPTION_REG
|
||||
|
||||
|
||||
|
||||
BCF STATUS,RP0 ; Bank 0
|
||||
BSF T2CON,TMR2ON ; PWM on
|
||||
BCF INTCON,GIE ; Global interrup enable
|
||||
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; MainLoop
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
Mainloop: BCF STATUS,RP0 ; Bank 0
|
||||
CLRWDT
|
||||
|
||||
;DECODE_PPM
|
||||
PPM_Lo: BTFSC PORTA,2
|
||||
GOTO PPM_Lo
|
||||
PPM_Hi: BTFSS PORTA,2
|
||||
GOTO PPM_Hi
|
||||
Clear16 TMR1H,TMR1L
|
||||
BSF T1CON,TMR1ON ; Timer1 on
|
||||
PPM_Loop: BTFSC PORTA,2
|
||||
GOTO PPM_Loop
|
||||
BCF T1CON,TMR1ON ; Timer1 off
|
||||
Comp16L TMR1H,TMR1L,.20000
|
||||
BTFSC STATUS,C
|
||||
GOTO Mainloop
|
||||
Comp16L TMR1H,TMR1L,.40000
|
||||
BTFSS STATUS,C
|
||||
GOTO Mainloop
|
||||
Sub16L TMR1H,TMR1L,.20000
|
||||
Comp16L TMR1H,TMR1L,.10000
|
||||
BTFSS STATUS,C
|
||||
GOTO PWM_Fwr
|
||||
GOTO PWM_Rev
|
||||
|
||||
PWM_Fwr: BCF CCP1CON,P1M1
|
||||
Sub16L TMR1H,TMR1L,.10000
|
||||
GOTO PWM_SetVal
|
||||
PWM_Rev: BSF CCP1CON,P1M1
|
||||
Sub16L TMR1H,TMR1L,.10000
|
||||
|
||||
PWM_SetVal:
|
||||
|
||||
|
||||
GOTO Mainloop
|
||||
END
|
||||
;==========================================================================================================
|
||||
; END
|
||||
;==========================================================================================================
|
||||
22
MainMotorDriver/ASM/MainMotorDriver.err
Executable file
22
MainMotorDriver/ASM/MainMotorDriver.err
Executable file
@ -0,0 +1,22 @@
|
||||
Warning[205] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 11 : Found directive in column 1. (include)
|
||||
Warning[207] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 190 : Found label after column 1. (iDivRepeat)
|
||||
Warning[207] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 193 : Found label after column 1. (iDivRepeat)
|
||||
Warning[207] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 193 : Found label after column 1. (iDivRepeat)
|
||||
Warning[207] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 193 : Found label after column 1. (iDivRepeat)
|
||||
Warning[207] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 193 : Found label after column 1. (iDivRepeat)
|
||||
Warning[207] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 193 : Found label after column 1. (iDivRepeat)
|
||||
Warning[207] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 193 : Found label after column 1. (iDivRepeat)
|
||||
Warning[207] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 193 : Found label after column 1. (iDivRepeat)
|
||||
Warning[207] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 193 : Found label after column 1. (iDivRepeat)
|
||||
Message[302] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 230 : Register in operand not in bank 0. Ensure that bank bits are correct.
|
||||
Message[302] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 231 : Register in operand not in bank 0. Ensure that bank bits are correct.
|
||||
Message[302] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 233 : Register in operand not in bank 0. Ensure that bank bits are correct.
|
||||
Message[302] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 235 : Register in operand not in bank 0. Ensure that bank bits are correct.
|
||||
Message[302] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 237 : Register in operand not in bank 0. Ensure that bank bits are correct.
|
||||
Message[302] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 239 : Register in operand not in bank 0. Ensure that bank bits are correct.
|
||||
Message[305] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 77 : Using default destination of 1 (file).
|
||||
Message[305] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 81 : Using default destination of 1 (file).
|
||||
Message[305] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 77 : Using default destination of 1 (file).
|
||||
Message[305] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 81 : Using default destination of 1 (file).
|
||||
Message[305] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 77 : Using default destination of 1 (file).
|
||||
Message[305] D:\-PROJECT-\WINGMAN\MAINMOTORDRIVER\ASM\MAINMOTORDRIVER.ASM 81 : Using default destination of 1 (file).
|
||||
840
MainMotorDriver/ASM/MainMotorDriver.lst
Executable file
840
MainMotorDriver/ASM/MainMotorDriver.lst
Executable file
@ -0,0 +1,840 @@
|
||||
MPASM 5.02 MAINMOTORDRIVER.ASM 3-29-2006 0:37:12 PAGE 1
|
||||
|
||||
|
||||
LOC OBJECT CODE LINE SOURCE TEXT
|
||||
VALUE
|
||||
|
||||
00001 ;=======================================================================================================
|
||||
===
|
||||
00002 ;
|
||||
00003 ; Wingman MainMotorDriver copyright 2005
|
||||
v1.0 (2005-04-22)
|
||||
00004 ;
|
||||
00005 ; Name: Christoffer Martinsson
|
||||
00006 ; E-mail: cm@wsm.se
|
||||
00007 ;
|
||||
00008 ;
|
||||
00009 ;=======================================================================================================
|
||||
===
|
||||
00010
|
||||
Warning[205]: Found directive in column 1. (include)
|
||||
00011 include P16F684.INC
|
||||
00001 LIST
|
||||
00002 ; P16F684.INC Standard Header File, Version 1.03 Microchip Technology, Inc.
|
||||
00379 LIST
|
||||
00012
|
||||
00013 ; Temp-registers
|
||||
00000020 00014 W_TEMP EQU 0x20 ; TempRegister for interrupt-routine
|
||||
00000021 00015 STATUS_TEMP EQU 0x21 ; TempRegister for interrupt-routine
|
||||
00000022 00016 DivRegH EQU 0x22 ; TempRegister for div-routine
|
||||
00000023 00017 DivRegL EQU 0x23 ; TempRegister for div-routine
|
||||
00000024 00018 SetPWM_Temp EQU 0x24
|
||||
00019
|
||||
00020 ; Time-definitions
|
||||
00004E20 00021 minPulseValue =.20000
|
||||
00009C40 00022 maxPulseValue =.40000
|
||||
00004E20 00023 ms1Value =.20000
|
||||
00002710 00024 ms05Value =.10000
|
||||
00025
|
||||
00026 ;=======================================================================================================
|
||||
===
|
||||
00027 ; Reset- and Interrupt-vectors
|
||||
00028 ;=======================================================================================================
|
||||
===
|
||||
0000 00029 ORG 0x0000
|
||||
0000 282C 00030 GOTO Main ;Reset-vector
|
||||
0004 00031 ORG 0x0004
|
||||
0004 2805 00032 GOTO Interrupt ;Interrupt-vector
|
||||
00033 ;=======================================================================================================
|
||||
===
|
||||
00034 ; Macro
|
||||
00035 ;=======================================================================================================
|
||||
===
|
||||
00036 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
00037 ; StoreWregInTemp
|
||||
00038 ;
|
||||
00039 ; Description: Store Status and working-register in temp-registers
|
||||
00040 ;
|
||||
00041 ; Input: -
|
||||
MPASM 5.02 MAINMOTORDRIVER.ASM 3-29-2006 0:37:12 PAGE 2
|
||||
|
||||
|
||||
LOC OBJECT CODE LINE SOURCE TEXT
|
||||
VALUE
|
||||
|
||||
00042 ; ChangedReg: W_TEMP,STATUS_TEMP
|
||||
00043 ; UsedReg: W,STATUS,W_TEMP,STATUS_TEMP
|
||||
00044 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
00045 StoreWregInTemp MACRO
|
||||
00046 MOVWF W_TEMP ;Copy W to TEMP register
|
||||
00047 SWAPF STATUS,W ;Swap status to be saved into W
|
||||
00048 CLRF STATUS ;bank 0, regardless of current bank, Cle
|
||||
ars IRP,RP1,RP0
|
||||
00049 MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
|
||||
00050 ENDM
|
||||
00051 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
00052 ; RestoreWregFromTemp
|
||||
00053 ;
|
||||
00054 ; Description: Restore Status and working-register from temp-registers
|
||||
00055 ;
|
||||
00056 ; Input: -
|
||||
00057 ; ChangedReg: W,STATUS
|
||||
00058 ; UsedReg: W,STATUS,W_TEMP,STATUS_TEMP
|
||||
00059 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
00060 RestoreWregFromTemp MACRO
|
||||
00061 SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W (sets bank to
|
||||
original state)
|
||||
00062 MOVWF STATUS ;Move W into Status register
|
||||
00063 SWAPF W_TEMP,F ;Swap W_TEMP
|
||||
00064 SWAPF W_TEMP,W ;Swap W_TEMP into W
|
||||
00065 ENDM
|
||||
00066 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
00067 ; Sub16L
|
||||
00068 ;
|
||||
00069 ; Description: Subtract literal from 16bit-register. Reg = Reg - Number, WITH VALID CARRY
|
||||
00070 ;
|
||||
00071 ; Input: RegH, RegL, Number
|
||||
00072 ; ChangedReg: C
|
||||
00073 ; UsedReg: W
|
||||
00074 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
00075 Sub16L MACRO RegH, RegL, Number
|
||||
00076 MOVLW low Number
|
||||
00077 SUBWF RegL
|
||||
00078 MOVLW high Number
|
||||
00079 ;BTFSS STATUS,C
|
||||
00080 ;INCFSZ high Number,W
|
||||
00081 SUBWF RegH
|
||||
00082 ENDM
|
||||
00083 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
00084 ; Set16L
|
||||
00085 ;
|
||||
00086 ; Description: Sets 16bit-register to literal. Reg = Number
|
||||
MPASM 5.02 MAINMOTORDRIVER.ASM 3-29-2006 0:37:12 PAGE 3
|
||||
|
||||
|
||||
LOC OBJECT CODE LINE SOURCE TEXT
|
||||
VALUE
|
||||
|
||||
00087 ;
|
||||
00088 ; Input: RegH, RegL, Number
|
||||
00089 ; ChangedReg: C
|
||||
00090 ; UsedReg: W
|
||||
00091 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
00092 Set16L MACRO RegH, RegL, Number
|
||||
00093 MOVLW low Number
|
||||
00094 MOVWF RegL
|
||||
00095 MOVLW high Number
|
||||
00096 MOVWF RegH
|
||||
00097 ENDM
|
||||
00098 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
00099 ; Clear16
|
||||
00100 ;
|
||||
00101 ; Description: Clear 16bit-register.
|
||||
00102 ;
|
||||
00103 ; Input: RegH, RegL
|
||||
00104 ; ChangedReg:
|
||||
00105 ; UsedReg:
|
||||
00106 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
00107 Clear16 MACRO RegH, RegL
|
||||
00108 CLRF RegH
|
||||
00109 CLRF RegL
|
||||
00110 ENDM
|
||||
00111 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
00112 ; Comp16L
|
||||
00113 ;
|
||||
00114 ; Description: Compare one 16bit-registers to literal if Reg1=Number then Z=1.
|
||||
00115 ;
|
||||
if Reg1<Number then C=1.
|
||||
00116 ;
|
||||
if Number<Reg1 then C=0.
|
||||
00117 ; Input: RegH, RegL, Number
|
||||
00118 ; ChangedReg: Z, C
|
||||
00119 ; UsedReg: W
|
||||
00120 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
00121 Comp16L MACRO RegH, RegL, Number
|
||||
00122 MOVF RegH,W
|
||||
00123 SUBLW high Number
|
||||
|
||||
00124 BTFSS STATUS,Z
|
||||
|
||||
00125 EXITM
|
||||
00126 MOVF RegL,W
|
||||
00127 SUBLW low Number
|
||||
00128 ENDM
|
||||
00129 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
MPASM 5.02 MAINMOTORDRIVER.ASM 3-29-2006 0:37:12 PAGE 4
|
||||
|
||||
|
||||
LOC OBJECT CODE LINE SOURCE TEXT
|
||||
VALUE
|
||||
|
||||
00130 ; SetPWM
|
||||
00131 ;
|
||||
00132 ; Description: Sets hardware PWM-output to 8bit register-value. PWM = Reg
|
||||
00133 ;
|
||||
|
||||
00134 ; Input: Reg
|
||||
00135 ; ChangedReg: CCP1CON(4,5), CCPR1L
|
||||
00136 ; UsedReg: W, CCP1CON(4,5), CCPR1L, Reg, SetPWM_Temp
|
||||
00137 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
00138 SetPWM MACRO Reg
|
||||
00139 BCF STATUS,C
|
||||
00140 MOVF Reg,W
|
||||
00141 ANDLW b'00000011'
|
||||
00142 MOVWF SetPWM_Temp
|
||||
00143 RLF SetPWM_Temp,F
|
||||
00144 RLF SetPWM_Temp,F
|
||||
00145 RLF SetPWM_Temp,F
|
||||
00146 RLF SetPWM_Temp,F
|
||||
00147 MOVF CCP1CON,W
|
||||
00148 ANDLW b'11001111'
|
||||
00149 IORWF SetPWM_Temp,W
|
||||
00150 MOVWF CCP1CON
|
||||
00151 MOVF Reg,W
|
||||
00152 ANDLW b'11111100'
|
||||
00153 MOVWF SetPWM_Temp
|
||||
00154 RRF SetPWM_Temp,F
|
||||
00155 RRF SetPWM_Temp,F
|
||||
00156 MOVF SetPWM_Temp,W
|
||||
00157 MOVWF CCPR1L
|
||||
00158 ENDM
|
||||
00159 ;=======================================================================================================
|
||||
===
|
||||
00160 ; Interrupt routines
|
||||
00161 ;=======================================================================================================
|
||||
===
|
||||
00162 Interrupt StoreWregInTemp
|
||||
0005 00A0 M MOVWF W_TEMP ;Copy W to TEMP register
|
||||
0006 0E03 M SWAPF STATUS,W ;Swap status to be saved into W
|
||||
0007 0183 M CLRF STATUS ;bank 0, regardless of current bank, Cle
|
||||
ars IRP,RP1,RP0
|
||||
0008 00A1 M MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
|
||||
00163 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
00164 ; Timer1_Int
|
||||
00165 ;
|
||||
00166 ; Description: Increment pulseIn counter-registers
|
||||
00167 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
0009 1283 00168 Timer1_Int BCF STATUS,RP0 ; Bank 0
|
||||
000A 1C0C 00169 BTFSS PIR1,TMR1IF
|
||||
000B 280E 00170 GOTO Int_Return
|
||||
000C 100C 00171 BCF PIR1,TMR1IF
|
||||
MPASM 5.02 MAINMOTORDRIVER.ASM 3-29-2006 0:37:12 PAGE 5
|
||||
|
||||
|
||||
LOC OBJECT CODE LINE SOURCE TEXT
|
||||
VALUE
|
||||
|
||||
000D 1010 00172 BCF T1CON,TMR1ON ; Timer1
|
||||
off
|
||||
00173 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
00174 Int_Return RestoreWregFromTemp
|
||||
000E 0E21 M SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W (sets bank to
|
||||
original state)
|
||||
000F 0083 M MOVWF STATUS ;Move W into Status register
|
||||
0010 0EA0 M SWAPF W_TEMP,F ;Swap W_TEMP
|
||||
0011 0E20 M SWAPF W_TEMP,W ;Swap W_TEMP into W
|
||||
0012 0009 00175 RETFIE
|
||||
00176
|
||||
00177 ;=======================================================================================================
|
||||
===
|
||||
00178 ; Sub-routines
|
||||
00179 ;=======================================================================================================
|
||||
===
|
||||
00180 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
00181 ; Div16byL
|
||||
00182 ;
|
||||
00183 ; Description: Divide a 16bit-register with a literal. DivReg = DivReg / W.
|
||||
00184 ;
|
||||
|
||||
00185 ; Input: DivRegH, DivRegL, W
|
||||
00186 ; ChangedReg: Z, C, DivRegH, DivRegL
|
||||
00187 ; UsedReg: W, DivRegH, DivRegL
|
||||
00188 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
0013 2026 00189 Div16byL CALL DivSkipHiShift
|
||||
Warning[207]: Found label after column 1. (iDivRepeat)
|
||||
00000008 00190 iDivRepeat =8
|
||||
00191 WHILE iDivRepeat
|
||||
0014 201F 00192 call DivCode
|
||||
Warning[207]: Found label after column 1. (iDivRepeat)
|
||||
00000007 00193 iDivRepeat--
|
||||
0015 201F 00192 call DivCode
|
||||
Warning[207]: Found label after column 1. (iDivRepeat)
|
||||
00000006 00193 iDivRepeat--
|
||||
0016 201F 00192 call DivCode
|
||||
Warning[207]: Found label after column 1. (iDivRepeat)
|
||||
00000005 00193 iDivRepeat--
|
||||
0017 201F 00192 call DivCode
|
||||
Warning[207]: Found label after column 1. (iDivRepeat)
|
||||
00000004 00193 iDivRepeat--
|
||||
0018 201F 00192 call DivCode
|
||||
Warning[207]: Found label after column 1. (iDivRepeat)
|
||||
00000003 00193 iDivRepeat--
|
||||
0019 201F 00192 call DivCode
|
||||
Warning[207]: Found label after column 1. (iDivRepeat)
|
||||
00000002 00193 iDivRepeat--
|
||||
001A 201F 00192 call DivCode
|
||||
Warning[207]: Found label after column 1. (iDivRepeat)
|
||||
MPASM 5.02 MAINMOTORDRIVER.ASM 3-29-2006 0:37:12 PAGE 6
|
||||
|
||||
|
||||
LOC OBJECT CODE LINE SOURCE TEXT
|
||||
VALUE
|
||||
|
||||
00000001 00193 iDivRepeat--
|
||||
001B 201F 00192 call DivCode
|
||||
Warning[207]: Found label after column 1. (iDivRepeat)
|
||||
00000000 00193 iDivRepeat--
|
||||
00194 ENDW
|
||||
001C 0DA3 00195 RLF DivRegL,F ; C << l
|
||||
o << C
|
||||
001D 1103 00196 BCF STATUS,Z
|
||||
001E 0008 00197 RETURN ; we are done!
|
||||
00198
|
||||
001F 0DA3 00199 DivCode RLF DivRegL,F ; C << lo << C
|
||||
0020 0DA2 00200 RLF DivRegH,F ; C << hi << C
|
||||
0021 1C03 00201 BTFSS STATUS,C ; if Carry
|
||||
0022 2826 00202 GOTO DivSkipHiShift
|
||||
0023 02A2 00203 SUBWF DivRegH,F ; hi-=w
|
||||
0024 1403 00204 BSF STATUS,C ; ignore carry
|
||||
0025 0008 00205 RETURN ; done
|
||||
00206 ; endif
|
||||
0026 00207 DivSkipHiShift
|
||||
0026 02A2 00208 SUBWF DivRegH,F ; hi-=w
|
||||
0027 1803 00209 BTFSC STATUS,C ; if carry set
|
||||
0028 0008 00210 RETURN ; done
|
||||
0029 07A2 00211 ADDWF DivRegH,F ; hi+=w
|
||||
002A 1003 00212 BCF STATUS,C ; clear carry
|
||||
002B 0008 00213 RETURN
|
||||
00214 ;=======================================================================================================
|
||||
===
|
||||
00215 ; Main
|
||||
00216 ;=======================================================================================================
|
||||
===
|
||||
002C 1283 00217 Main BCF STATUS,RP0 ; Bank 0
|
||||
002D 0187 00218 CLRF PORTC ; Clear
|
||||
PORTC
|
||||
002E 0185 00219 CLRF PORTA ; Clear
|
||||
PORTA
|
||||
002F 3007 00220 MOVLW 0x07
|
||||
0030 0099 00221 MOVWF CMCON0 ; Compar
|
||||
ator OFF
|
||||
0031 0193 00222 CLRF CCPR1L
|
||||
0032 304C 00223 MOVLW b'01001100'
|
||||
0033 0095 00224 MOVWF CCP1CON
|
||||
0034 3081 00225 MOVLW b'10000001'
|
||||
0035 009F 00226 MOVWF ADCON0
|
||||
00227
|
||||
0036 1683 00228 BSF STATUS,RP0 ; Bank 1
|
||||
0037 300D 00229 MOVLW b'00001101'
|
||||
Message[302]: Register in operand not in bank 0. Ensure that bank bits are correct.
|
||||
0038 0085 00230 MOVWF TRISA
|
||||
Message[302]: Register in operand not in bank 0. Ensure that bank bits are correct.
|
||||
0039 0187 00231 CLRF TRISC
|
||||
003A 3001 00232 MOVLW b'00000001'
|
||||
Message[302]: Register in operand not in bank 0. Ensure that bank bits are correct.
|
||||
003B 0091 00233 MOVWF ANSEL ; All pi
|
||||
MPASM 5.02 MAINMOTORDRIVER.ASM 3-29-2006 0:37:12 PAGE 7
|
||||
|
||||
|
||||
LOC OBJECT CODE LINE SOURCE TEXT
|
||||
VALUE
|
||||
|
||||
ns to digital I/O except AN0
|
||||
003C 303F 00234 MOVLW 0x3F
|
||||
Message[302]: Register in operand not in bank 0. Ensure that bank bits are correct.
|
||||
003D 0092 00235 MOVWF PR2
|
||||
003E 3020 00236 MOVLW b'00100000'
|
||||
Message[302]: Register in operand not in bank 0. Ensure that bank bits are correct.
|
||||
003F 009F 00237 MOVWF ADCON1
|
||||
0040 30CF 00238 MOVLW b'11001111'
|
||||
Message[302]: Register in operand not in bank 0. Ensure that bank bits are correct.
|
||||
0041 0081 00239 MOVWF OPTION_REG
|
||||
00240
|
||||
0042 1283 00241 BCF STATUS,RP0 ; Bank 0
|
||||
0043 1512 00242 BSF T2CON,TMR2ON ; PWM on
|
||||
0044 178B 00243 BSF INTCON,GIE
|
||||
; Global interrup enable
|
||||
00244
|
||||
00245 ; MOVLW low .30000
|
||||
00246 ; MOVWF TMR1L
|
||||
00247 ; MOVLW high .30000
|
||||
00248 ; MOVWF TMR1H
|
||||
00249
|
||||
00250 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
00251 ; MainLoop
|
||||
00252 ;-------------------------------------------------------------------------------------------------------
|
||||
---
|
||||
0045 1283 00253 Mainloop: BCF STATUS,RP0 ; Bank 0
|
||||
0046 0064 00254 CLRWDT
|
||||
00255
|
||||
00256 ;DECODE_PPM
|
||||
0047 1905 00257 PPM_Lo: BTFSC PORTA,2 ; Wait for pulse
|
||||
to go low
|
||||
0048 2847 00258 GOTO PPM_Lo
|
||||
0049 1D05 00259 PPM_Hi: BTFSS PORTA,2 ; Wait for pulse
|
||||
to go high (start measuring)
|
||||
004A 2849 00260 GOTO PPM_Hi
|
||||
00261 Clear16 TMR1H,TMR1L ; Clear
|
||||
Timer1 countervalue
|
||||
004B 018F M CLRF TMR1H
|
||||
004C 018E M CLRF TMR1L
|
||||
004D 1410 00262 BSF T1CON,TMR1ON ; Start
|
||||
Timer1
|
||||
004E 1905 00263 PPM_Loop: BTFSC PORTA,2 ; Wait for pulse to go l
|
||||
ow (stop measuring)
|
||||
004F 284E 00264 GOTO PPM_Loop
|
||||
0050 1010 00265 BCF T1CON,TMR1ON ; Stop Timer1
|
||||
|
||||
00266 ; Comp16L TMR1H,TMR1L,minPulseValue
|
||||
00267 ; BTFSC STATUS,C ; If cou
|
||||
nter < minPulseValue (~1ms)
|
||||
00268 ; GOTO Mainloop ; then g
|
||||
oto Mainloop
|
||||
00269 ; Comp16L TMR1H,TMR1L,maxPulseValue
|
||||
MPASM 5.02 MAINMOTORDRIVER.ASM 3-29-2006 0:37:12 PAGE 8
|
||||
|
||||
|
||||
LOC OBJECT CODE LINE SOURCE TEXT
|
||||
VALUE
|
||||
|
||||
00270 ; BTFSS STATUS,C ; else I
|
||||
f counter > maxPulseValue (~2ms)
|
||||
00271 ; GOTO Mainloop ; then g
|
||||
oto Mainloop
|
||||
00272 Sub16L TMR1H,TMR1L,ms1Value ; else counter-value - 1
|
||||
ms
|
||||
0051 3020 M MOVLW low ms1Value
|
||||
Message[305]: Using default destination of 1 (file).
|
||||
0052 028E M SUBWF TMR1L
|
||||
0053 304E M MOVLW high ms1Value
|
||||
M ;BTFSS STATUS,C
|
||||
M ;INCFSZ high Number,W
|
||||
Message[305]: Using default destination of 1 (file).
|
||||
0054 028F M SUBWF TMR1H
|
||||
00273 Comp16L TMR1H,TMR1L,ms05Value
|
||||
0055 080F M MOVF TMR1H,W
|
||||
0056 3C27 M SUBLW high ms05Value
|
||||
|
||||
0057 1D03 M BTFSS STATUS,Z
|
||||
|
||||
M EXITM
|
||||
0058 1C03 00274 BTFSS STATUS,C ; If cou
|
||||
nter > 0,5ms
|
||||
0059 285B 00275 GOTO PWM_Fwr ; then g
|
||||
oto PWM_forward
|
||||
005A 2861 00276 GOTO PWM_Rev ; else g
|
||||
oto PWN_reverse
|
||||
00277
|
||||
005B 1395 00278 PWM_Fwr: BCF CCP1CON,P1M1 ; Set H-bridge i
|
||||
n forward-mode
|
||||
00279 Sub16L TMR1H,TMR1L,ms05Value ; counter-value - 0,5ms
|
||||
005C 3010 M MOVLW low ms05Value
|
||||
Message[305]: Using default destination of 1 (file).
|
||||
005D 028E M SUBWF TMR1L
|
||||
005E 3027 M MOVLW high ms05Value
|
||||
M ;BTFSS STATUS,C
|
||||
M ;INCFSZ high Number,W
|
||||
Message[305]: Using default destination of 1 (file).
|
||||
005F 028F M SUBWF TMR1H
|
||||
0060 2869 00280 GOTO PWM_SetVal ; goto P
|
||||
WM_SetValue
|
||||
0061 1795 00281 PWM_Rev: BSF CCP1CON,P1M1 ; Set H-bridge i
|
||||
n reverse-mode
|
||||
0062 30FF 00282 MOVLW 0xFF
|
||||
0063 068F 00283 XORWF TMR1H,F ; Invert
|
||||
counterH
|
||||
0064 068E 00284 XORWF TMR1L,F ; Invert
|
||||
counterL
|
||||
00285 Sub16L TMR1H,TMR1L,(0xFFFF-ms05Value) ; Inverted counter-value - (6553
|
||||
5-0,5ms)
|
||||
0065 30EF M MOVLW low (0xFFFF-ms05Value)
|
||||
Message[305]: Using default destination of 1 (file).
|
||||
0066 028E M SUBWF TMR1L
|
||||
MPASM 5.02 MAINMOTORDRIVER.ASM 3-29-2006 0:37:12 PAGE 9
|
||||
|
||||
|
||||
LOC OBJECT CODE LINE SOURCE TEXT
|
||||
VALUE
|
||||
|
||||
0067 30D8 M MOVLW high (0xFFFF-ms05Value)
|
||||
M ;BTFSS STATUS,C
|
||||
M ;INCFSZ high Number,W
|
||||
Message[305]: Using default destination of 1 (file).
|
||||
0068 028F M SUBWF TMR1H
|
||||
00286
|
||||
0069 080F 00287 PWM_SetVal: MOVF TMR1H,W ; Divide by 79..
|
||||
.
|
||||
006A 00A2 00288 MOVWF DivRegH ; Load d
|
||||
iv-routine with countervalue
|
||||
006B 080E 00289 MOVF TMR1L,W
|
||||
006C 00A3 00290 MOVWF DivRegL ; Load d
|
||||
iv-routine with countervalue
|
||||
006D 3028 00291 MOVLW ((ms05Value/0xFF)+1) ; Load div-routine with
|
||||
divide-value
|
||||
006E 2013 00292 CALL Div16byL ; Divide
|
||||
!
|
||||
00293
|
||||
00294 SetPWM DivRegL
|
||||
006F 1003 M BCF STATUS,C
|
||||
0070 0823 M MOVF DivRegL,W
|
||||
0071 3903 M ANDLW b'00000011'
|
||||
0072 00A4 M MOVWF SetPWM_Temp
|
||||
0073 0DA4 M RLF SetPWM_Temp,F
|
||||
0074 0DA4 M RLF SetPWM_Temp,F
|
||||
0075 0DA4 M RLF SetPWM_Temp,F
|
||||
0076 0DA4 M RLF SetPWM_Temp,F
|
||||
0077 0815 M MOVF CCP1CON,W
|
||||
0078 39CF M ANDLW b'11001111'
|
||||
0079 0424 M IORWF SetPWM_Temp,W
|
||||
007A 0095 M MOVWF CCP1CON
|
||||
007B 0823 M MOVF DivRegL,W
|
||||
007C 39FC M ANDLW b'11111100'
|
||||
007D 00A4 M MOVWF SetPWM_Temp
|
||||
007E 0CA4 M RRF SetPWM_Temp,F
|
||||
007F 0CA4 M RRF SetPWM_Temp,F
|
||||
0080 0824 M MOVF SetPWM_Temp,W
|
||||
0081 0093 M MOVWF CCPR1L
|
||||
00295
|
||||
0082 2845 00296 GOTO Mainloop
|
||||
00297 END
|
||||
MPASM 5.02 MAINMOTORDRIVER.ASM 3-29-2006 0:37:12 PAGE 10
|
||||
|
||||
|
||||
SYMBOL TABLE
|
||||
LABEL VALUE
|
||||
|
||||
ADCON0 0000001F
|
||||
ADCON1 0000009F
|
||||
ADCS0 00000004
|
||||
ADCS1 00000005
|
||||
ADCS2 00000006
|
||||
ADFM 00000007
|
||||
ADIE 00000006
|
||||
ADIF 00000006
|
||||
ADON 00000000
|
||||
ADRESH 0000001E
|
||||
ADRESL 0000009E
|
||||
ANS0 00000000
|
||||
ANS1 00000001
|
||||
ANS2 00000002
|
||||
ANS3 00000003
|
||||
ANS4 00000004
|
||||
ANS5 00000005
|
||||
ANS6 00000006
|
||||
ANS7 00000007
|
||||
ANSEL 00000091
|
||||
C 00000000
|
||||
C1IE 00000003
|
||||
C1IF 00000003
|
||||
C1INV 00000004
|
||||
C1OUT 00000006
|
||||
C2IE 00000004
|
||||
C2IF 00000004
|
||||
C2INV 00000005
|
||||
C2OUT 00000007
|
||||
C2SYNC 00000000
|
||||
CCP1CON 00000015
|
||||
CCP1IE 00000005
|
||||
CCP1IF 00000005
|
||||
CCP1M0 00000000
|
||||
CCP1M1 00000001
|
||||
CCP1M2 00000002
|
||||
CCP1M3 00000003
|
||||
CCPR1H 00000014
|
||||
CCPR1L 00000013
|
||||
CHS0 00000002
|
||||
CHS1 00000003
|
||||
CHS2 00000004
|
||||
CIS 00000003
|
||||
CM0 00000000
|
||||
CM1 00000001
|
||||
CM2 00000002
|
||||
CMCON0 00000019
|
||||
CMCON1 0000001A
|
||||
Clear16
|
||||
Comp16L
|
||||
DC 00000001
|
||||
DC1B0 00000004
|
||||
DC1B1 00000005
|
||||
MPASM 5.02 MAINMOTORDRIVER.ASM 3-29-2006 0:37:12 PAGE 11
|
||||
|
||||
|
||||
SYMBOL TABLE
|
||||
LABEL VALUE
|
||||
|
||||
Div16byL 00000013
|
||||
DivCode 0000001F
|
||||
DivRegH 00000022
|
||||
DivRegL 00000023
|
||||
DivSkipHiShift 00000026
|
||||
ECCPAS 00000017
|
||||
ECCPAS0 00000004
|
||||
ECCPAS1 00000005
|
||||
ECCPAS2 00000006
|
||||
ECCPASE 00000007
|
||||
EEADR 0000009B
|
||||
EECON1 0000009C
|
||||
EECON2 0000009D
|
||||
EEDAT 0000009A
|
||||
EEDATA 0000009A
|
||||
EEIE 00000007
|
||||
EEIF 00000007
|
||||
F 00000001
|
||||
FSR 00000004
|
||||
GIE 00000007
|
||||
GO 00000001
|
||||
GO_DONE 00000001
|
||||
HTS 00000002
|
||||
INDF 00000000
|
||||
INTCON 0000000B
|
||||
INTE 00000004
|
||||
INTEDG 00000006
|
||||
INTF 00000001
|
||||
IOC 00000096
|
||||
IOC0 00000000
|
||||
IOC1 00000001
|
||||
IOC2 00000002
|
||||
IOC3 00000003
|
||||
IOC4 00000004
|
||||
IOC5 00000005
|
||||
IOCA 00000096
|
||||
IOCA0 00000000
|
||||
IOCA1 00000001
|
||||
IOCA2 00000002
|
||||
IOCA3 00000003
|
||||
IOCA4 00000004
|
||||
IOCA5 00000005
|
||||
IRCF0 00000004
|
||||
IRCF1 00000005
|
||||
IRCF2 00000006
|
||||
IRP 00000007
|
||||
Int_Return 0000000E
|
||||
Interrupt 00000005
|
||||
LTS 00000001
|
||||
Main 0000002C
|
||||
Mainloop 00000045
|
||||
NOT_BOD 00000000
|
||||
NOT_DONE 00000001
|
||||
MPASM 5.02 MAINMOTORDRIVER.ASM 3-29-2006 0:37:12 PAGE 12
|
||||
|
||||
|
||||
SYMBOL TABLE
|
||||
LABEL VALUE
|
||||
|
||||
NOT_PD 00000003
|
||||
NOT_POR 00000001
|
||||
NOT_RAPU 00000007
|
||||
NOT_T1SYNC 00000002
|
||||
NOT_TO 00000004
|
||||
OPTION_REG 00000081
|
||||
OSCCON 0000008F
|
||||
OSCTUNE 00000090
|
||||
OSFIE 00000002
|
||||
OSFIF 00000002
|
||||
OSTS 00000003
|
||||
P1M0 00000006
|
||||
P1M1 00000007
|
||||
PCL 00000002
|
||||
PCLATH 0000000A
|
||||
PCON 0000008E
|
||||
PDC0 00000000
|
||||
PDC1 00000001
|
||||
PDC2 00000002
|
||||
PDC3 00000003
|
||||
PDC4 00000004
|
||||
PDC5 00000005
|
||||
PDC6 00000006
|
||||
PEIE 00000006
|
||||
PIE1 0000008C
|
||||
PIR1 0000000C
|
||||
PORTA 00000005
|
||||
PORTC 00000007
|
||||
PPM_Hi 00000049
|
||||
PPM_Lo 00000047
|
||||
PPM_Loop 0000004E
|
||||
PR2 00000092
|
||||
PRSEN 00000007
|
||||
PS0 00000000
|
||||
PS1 00000001
|
||||
PS2 00000002
|
||||
PSA 00000003
|
||||
PSSAC0 00000002
|
||||
PSSAC1 00000003
|
||||
PSSBD0 00000000
|
||||
PSSBD1 00000001
|
||||
PWM1CON 00000016
|
||||
PWM_Fwr 0000005B
|
||||
PWM_Rev 00000061
|
||||
PWM_SetVal 00000069
|
||||
RAIE 00000003
|
||||
RAIF 00000000
|
||||
RD 00000000
|
||||
RP0 00000005
|
||||
RP1 00000006
|
||||
RestoreWregFromTemp
|
||||
SBODEN 00000004
|
||||
SCS 00000000
|
||||
MPASM 5.02 MAINMOTORDRIVER.ASM 3-29-2006 0:37:12 PAGE 13
|
||||
|
||||
|
||||
SYMBOL TABLE
|
||||
LABEL VALUE
|
||||
|
||||
STATUS 00000003
|
||||
STATUS_TEMP 00000021
|
||||
SWDTEN 00000000
|
||||
Set16L
|
||||
SetPWM
|
||||
SetPWM_Temp 00000024
|
||||
StoreWregInTemp
|
||||
Sub16L
|
||||
T0CS 00000005
|
||||
T0IE 00000005
|
||||
T0IF 00000002
|
||||
T0SE 00000004
|
||||
T1CKPS0 00000004
|
||||
T1CKPS1 00000005
|
||||
T1CON 00000010
|
||||
T1GINV 00000007
|
||||
T1GSS 00000001
|
||||
T1IE 00000000
|
||||
T1IF 00000000
|
||||
T1OSCEN 00000003
|
||||
T2CKPS0 00000000
|
||||
T2CKPS1 00000001
|
||||
T2CON 00000012
|
||||
T2IE 00000001
|
||||
T2IF 00000001
|
||||
TMR0 00000001
|
||||
TMR1CS 00000001
|
||||
TMR1GE 00000006
|
||||
TMR1H 0000000F
|
||||
TMR1IE 00000000
|
||||
TMR1IF 00000000
|
||||
TMR1L 0000000E
|
||||
TMR1ON 00000000
|
||||
TMR2 00000011
|
||||
TMR2IE 00000001
|
||||
TMR2IF 00000001
|
||||
TMR2ON 00000002
|
||||
TOUTPS0 00000003
|
||||
TOUTPS1 00000004
|
||||
TOUTPS2 00000005
|
||||
TOUTPS3 00000006
|
||||
TRISA 00000085
|
||||
TRISC 00000087
|
||||
TUN0 00000000
|
||||
TUN1 00000001
|
||||
TUN2 00000002
|
||||
TUN3 00000003
|
||||
TUN4 00000004
|
||||
Timer1_Int 00000009
|
||||
ULPWUE 00000005
|
||||
VCFG 00000006
|
||||
VR0 00000000
|
||||
VR1 00000001
|
||||
MPASM 5.02 MAINMOTORDRIVER.ASM 3-29-2006 0:37:12 PAGE 14
|
||||
|
||||
|
||||
SYMBOL TABLE
|
||||
LABEL VALUE
|
||||
|
||||
VR2 00000002
|
||||
VR3 00000003
|
||||
VRCON 00000099
|
||||
VREN 00000007
|
||||
VRR 00000005
|
||||
W 00000000
|
||||
WDTCON 00000018
|
||||
WDTPS0 00000001
|
||||
WDTPS1 00000002
|
||||
WDTPS2 00000003
|
||||
WDTPS3 00000004
|
||||
WPU 00000095
|
||||
WPUA 00000095
|
||||
WR 00000001
|
||||
WREN 00000002
|
||||
WRERR 00000003
|
||||
W_TEMP 00000020
|
||||
Z 00000002
|
||||
_BOD_NSLEEP 00003EFF
|
||||
_BOD_OFF 00003CFF
|
||||
_BOD_ON 00003FFF
|
||||
_BOD_SBODEN 00003DFF
|
||||
_CPD_OFF 00003FFF
|
||||
_CPD_ON 00003F7F
|
||||
_CP_OFF 00003FFF
|
||||
_CP_ON 00003FBF
|
||||
_EC_OSC 00003FFB
|
||||
_EXTRC 00003FFF
|
||||
_EXTRCIO 00003FFE
|
||||
_EXTRC_OSC_CLKOUT 00003FFF
|
||||
_EXTRC_OSC_NOCLKOUT 00003FFE
|
||||
_FCMEN_OFF 000037FF
|
||||
_FCMEN_ON 00003FFF
|
||||
_HS_OSC 00003FFA
|
||||
_IESO_OFF 00003BFF
|
||||
_IESO_ON 00003FFF
|
||||
_INTOSC 00003FFD
|
||||
_INTOSCIO 00003FFC
|
||||
_INTRC_OSC_CLKOUT 00003FFD
|
||||
_INTRC_OSC_NOCLKOUT 00003FFC
|
||||
_LP_OSC 00003FF8
|
||||
_MCLRE_OFF 00003FDF
|
||||
_MCLRE_ON 00003FFF
|
||||
_PWRTE_OFF 00003FFF
|
||||
_PWRTE_ON 00003FEF
|
||||
_WDT_OFF 00003FF7
|
||||
_WDT_ON 00003FFF
|
||||
_XT_OSC 00003FF9
|
||||
__16F684 00000001
|
||||
iDivRepeat 00000000
|
||||
maxPulseValue 00009C40
|
||||
minPulseValue 00004E20
|
||||
ms05Value 00002710
|
||||
MPASM 5.02 MAINMOTORDRIVER.ASM 3-29-2006 0:37:12 PAGE 15
|
||||
|
||||
|
||||
SYMBOL TABLE
|
||||
LABEL VALUE
|
||||
|
||||
ms1Value 00004E20
|
||||
|
||||
|
||||
MEMORY USAGE MAP ('X' = Used, '-' = Unused)
|
||||
|
||||
0000 : X---XXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
|
||||
0040 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
|
||||
0080 : XXX------------- ---------------- ---------------- ----------------
|
||||
|
||||
All other memory blocks unused.
|
||||
|
||||
Program Memory Words Used: 128
|
||||
Program Memory Words Free: 1920
|
||||
|
||||
|
||||
Errors : 0
|
||||
Warnings : 10 reported, 0 suppressed
|
||||
Messages : 12 reported, 0 suppressed
|
||||
|
||||
|
||||
28
MainMotorDriver/ASM/MainMotorDriver.mcp
Executable file
28
MainMotorDriver/ASM/MainMotorDriver.mcp
Executable file
@ -0,0 +1,28 @@
|
||||
[HEADER]
|
||||
magic_cookie={66E99B07-E706-4689-9E80-9B2582898A13}
|
||||
file_version=1.0
|
||||
[PATH_INFO]
|
||||
dir_src=
|
||||
dir_bin=
|
||||
dir_tmp=
|
||||
dir_sin=
|
||||
dir_inc=
|
||||
dir_lib=
|
||||
dir_lkr=
|
||||
[CAT_FILTERS]
|
||||
filter_src=*.asm
|
||||
filter_inc=*.h;*.inc
|
||||
filter_obj=*.o
|
||||
filter_lib=*.lib
|
||||
filter_lkr=*.lkr
|
||||
[OTHER_FILES]
|
||||
file_000=no
|
||||
[FILE_INFO]
|
||||
file_000=MainMotorDriver.asm
|
||||
[SUITE_INFO]
|
||||
suite_guid={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484}
|
||||
suite_state=
|
||||
[TOOL_SETTINGS]
|
||||
TS{DD2213A8-6310-47B1-8376-9430CDFC013F}=
|
||||
TS{BFD27FBA-4A02-4C0E-A5E5-B812F3E7707C}=/o"$(TARGETBASE).cof"
|
||||
TS{ADE93A55-C7C7-4D4D-A4BA-59305F7D0391}=
|
||||
49
MainMotorDriver/ASM/MainMotorDriver.mcs
Executable file
49
MainMotorDriver/ASM/MainMotorDriver.mcs
Executable file
@ -0,0 +1,49 @@
|
||||
[Header]
|
||||
MagicCookie={0b13fe8c-dfe0-40eb-8900-6712719559a7}
|
||||
Version=1.0
|
||||
[File000]
|
||||
Location=MainMotorDriver.err
|
||||
Folder=Intermediary
|
||||
DeviceName=PIC16F684
|
||||
LanguageToolSuiteID={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484}
|
||||
LanguageToolID={49D3CA3F-D9A3-4518-9943-226A347E8CC7}
|
||||
LanguageToolLocation=C:\Program Files\Microchip\MPASM Suite\MPAsmWin.exe
|
||||
PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)||$(INCDIR)||$(LIBDIR)||$(LKRDIR)||
|
||||
SOLK=<src>|MainMotorDriver.asm||<obj>||<lib>||<lkr>||
|
||||
SuiteArgsString=
|
||||
ToolArgsString=
|
||||
[File001]
|
||||
Location=D:\-Project-\Wingman\MainMotorDriver\ASM\MainMotorDriver.cod
|
||||
Folder=Output
|
||||
DeviceName=PIC16F684
|
||||
LanguageToolSuiteID={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484}
|
||||
LanguageToolID={49D3CA3F-D9A3-4518-9943-226A347E8CC7}
|
||||
LanguageToolLocation=C:\Program Files\Microchip\MPASM Suite\MPAsmWin.exe
|
||||
PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)||$(INCDIR)||$(LIBDIR)||$(LKRDIR)||
|
||||
SOLK=<src>|MainMotorDriver.asm||<obj>||<lib>||<lkr>||
|
||||
SuiteArgsString=
|
||||
ToolArgsString=
|
||||
[File002]
|
||||
Location=D:\-Project-\Wingman\MainMotorDriver\ASM\MainMotorDriver.hex
|
||||
Folder=Output
|
||||
DeviceName=PIC16F684
|
||||
LanguageToolSuiteID={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484}
|
||||
LanguageToolID={49D3CA3F-D9A3-4518-9943-226A347E8CC7}
|
||||
LanguageToolLocation=C:\Program Files\Microchip\MPASM Suite\MPAsmWin.exe
|
||||
PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)||$(INCDIR)||$(LIBDIR)||$(LKRDIR)||
|
||||
SOLK=<src>|MainMotorDriver.asm||<obj>||<lib>||<lkr>||
|
||||
SuiteArgsString=
|
||||
ToolArgsString=
|
||||
[File003]
|
||||
Location=MainMotorDriver.lst
|
||||
Folder=Output
|
||||
DeviceName=PIC16F684
|
||||
LanguageToolSuiteID={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484}
|
||||
LanguageToolID={49D3CA3F-D9A3-4518-9943-226A347E8CC7}
|
||||
LanguageToolLocation=C:\Program Files\Microchip\MPASM Suite\MPAsmWin.exe
|
||||
PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)||$(INCDIR)||$(LIBDIR)||$(LKRDIR)||
|
||||
SOLK=<src>|MainMotorDriver.asm||<obj>||<lib>||<lkr>||
|
||||
SuiteArgsString=
|
||||
ToolArgsString=
|
||||
[TOOL_LOC_STAMPS]
|
||||
tool_loc{49D3CA3F-D9A3-4518-9943-226A347E8CC7}=C:\Program Files\Microchip\MPASM Suite\MPAsmWin.exe
|
||||
BIN
MainMotorDriver/ASM/MainMotorDriver.mcw
Executable file
BIN
MainMotorDriver/ASM/MainMotorDriver.mcw
Executable file
Binary file not shown.
0
MainMotorDriver/ASM/MainMotorDriver.tagsrc
Executable file
0
MainMotorDriver/ASM/MainMotorDriver.tagsrc
Executable file
379
MainMotorDriver/ASM/P16F684.INC
Executable file
379
MainMotorDriver/ASM/P16F684.INC
Executable file
@ -0,0 +1,379 @@
|
||||
LIST
|
||||
; P16F684.INC Standard Header File, Version 1.03 Microchip Technology, Inc.
|
||||
NOLIST
|
||||
|
||||
; This header file defines configurations, registers, and other useful bits of
|
||||
; information for the PIC16F684 microcontroller. These names are taken to match
|
||||
; the data sheets as closely as possible.
|
||||
|
||||
; Note that the processor must be selected before this file is
|
||||
; included. The processor may be selected the following ways:
|
||||
|
||||
; 1. Command line switch:
|
||||
; C:\ MPASM MYFILE.ASM /PIC16F684
|
||||
; 2. LIST directive in the source file
|
||||
; LIST P=PIC16F684
|
||||
; 3. Processor Type entry in the MPASM full-screen interface
|
||||
|
||||
;==========================================================================
|
||||
;
|
||||
; Revision History
|
||||
;
|
||||
;==========================================================================
|
||||
;1.00 03/20/03 Original
|
||||
;1.01 08/04/03 Updated CMCON1 address
|
||||
;1.02 08/05/03 Updated names to match datasheet
|
||||
;1.03 08/11/03 Updated ULPWUE bit name to match datasheet
|
||||
;==========================================================================
|
||||
;
|
||||
; Verify Processor
|
||||
;
|
||||
;==========================================================================
|
||||
|
||||
IFNDEF __16F684
|
||||
MESSG "Processor-header file mismatch. Verify selected processor."
|
||||
ENDIF
|
||||
|
||||
;==========================================================================
|
||||
;
|
||||
; Register Definitions
|
||||
;
|
||||
;==========================================================================
|
||||
|
||||
W EQU H'0000'
|
||||
F EQU H'0001'
|
||||
|
||||
;----- Register Files------------------------------------------------------
|
||||
|
||||
INDF EQU H'0000'
|
||||
TMR0 EQU H'0001'
|
||||
PCL EQU H'0002'
|
||||
STATUS EQU H'0003'
|
||||
FSR EQU H'0004'
|
||||
PORTA EQU H'0005'
|
||||
|
||||
PORTC EQU H'0007'
|
||||
|
||||
PCLATH EQU H'000A'
|
||||
INTCON EQU H'000B'
|
||||
PIR1 EQU H'000C'
|
||||
|
||||
TMR1L EQU H'000E'
|
||||
TMR1H EQU H'000F'
|
||||
T1CON EQU H'0010'
|
||||
TMR2 EQU H'0011'
|
||||
T2CON EQU H'0012'
|
||||
CCPR1L EQU H'0013'
|
||||
CCPR1H EQU H'0014'
|
||||
CCP1CON EQU H'0015'
|
||||
PWM1CON EQU H'0016'
|
||||
ECCPAS EQU H'0017'
|
||||
WDTCON EQU H'0018'
|
||||
CMCON0 EQU H'0019'
|
||||
CMCON1 EQU H'001A'
|
||||
|
||||
ADRESH EQU H'001E'
|
||||
ADCON0 EQU H'001F'
|
||||
|
||||
|
||||
OPTION_REG EQU H'0081'
|
||||
|
||||
TRISA EQU H'0085'
|
||||
TRISC EQU H'0087'
|
||||
|
||||
PIE1 EQU H'008C'
|
||||
|
||||
PCON EQU H'008E'
|
||||
OSCCON EQU H'008F'
|
||||
OSCTUNE EQU H'0090'
|
||||
ANSEL EQU H'0091'
|
||||
PR2 EQU H'0092'
|
||||
|
||||
WPU EQU H'0095'
|
||||
WPUA EQU H'0095'
|
||||
IOC EQU H'0096'
|
||||
IOCA EQU H'0096'
|
||||
|
||||
VRCON EQU H'0099'
|
||||
EEDAT EQU H'009A'
|
||||
EEDATA EQU H'009A'
|
||||
EEADR EQU H'009B'
|
||||
EECON1 EQU H'009C'
|
||||
EECON2 EQU H'009D'
|
||||
ADRESL EQU H'009E'
|
||||
ADCON1 EQU H'009F'
|
||||
|
||||
|
||||
;----- STATUS Bits --------------------------------------------------------
|
||||
|
||||
IRP EQU H'0007'
|
||||
RP1 EQU H'0006'
|
||||
RP0 EQU H'0005'
|
||||
NOT_TO EQU H'0004'
|
||||
NOT_PD EQU H'0003'
|
||||
Z EQU H'0002'
|
||||
DC EQU H'0001'
|
||||
C EQU H'0000'
|
||||
|
||||
;----- INTCON Bits --------------------------------------------------------
|
||||
|
||||
GIE EQU H'0007'
|
||||
PEIE EQU H'0006'
|
||||
T0IE EQU H'0005'
|
||||
INTE EQU H'0004'
|
||||
RAIE EQU H'0003'
|
||||
T0IF EQU H'0002'
|
||||
INTF EQU H'0001'
|
||||
RAIF EQU H'0000'
|
||||
|
||||
;----- PIR1 Bits ----------------------------------------------------------
|
||||
|
||||
EEIF EQU H'0007'
|
||||
ADIF EQU H'0006'
|
||||
CCP1IF EQU H'0005'
|
||||
C2IF EQU H'0004'
|
||||
C1IF EQU H'0003'
|
||||
OSFIF EQU H'0002'
|
||||
T2IF EQU H'0001'
|
||||
TMR2IF EQU H'0001'
|
||||
T1IF EQU H'0000'
|
||||
TMR1IF EQU H'0000'
|
||||
|
||||
;----- T1CON Bits ---------------------------------------------------------
|
||||
|
||||
T1GINV EQU H'0007'
|
||||
TMR1GE EQU H'0006'
|
||||
T1CKPS1 EQU H'0005'
|
||||
T1CKPS0 EQU H'0004'
|
||||
T1OSCEN EQU H'0003'
|
||||
NOT_T1SYNC EQU H'0002'
|
||||
TMR1CS EQU H'0001'
|
||||
TMR1ON EQU H'0000'
|
||||
|
||||
;----- T2CON Bits ---------------------------------------------------------
|
||||
|
||||
TOUTPS3 EQU H'0006'
|
||||
TOUTPS2 EQU H'0005'
|
||||
TOUTPS1 EQU H'0004'
|
||||
TOUTPS0 EQU H'0003'
|
||||
TMR2ON EQU H'0002'
|
||||
T2CKPS1 EQU H'0001'
|
||||
T2CKPS0 EQU H'0000'
|
||||
|
||||
;----- CCP1CON Bits -------------------------------------------------------
|
||||
|
||||
P1M1 EQU H'0007'
|
||||
P1M0 EQU H'0006'
|
||||
DC1B1 EQU H'0005'
|
||||
DC1B0 EQU H'0004'
|
||||
CCP1M3 EQU H'0003'
|
||||
CCP1M2 EQU H'0002'
|
||||
CCP1M1 EQU H'0001'
|
||||
CCP1M0 EQU H'0000'
|
||||
|
||||
;----- PWM1CON Bits -------------------------------------------------------
|
||||
|
||||
PRSEN EQU H'0007'
|
||||
PDC6 EQU H'0006'
|
||||
PDC5 EQU H'0005'
|
||||
PDC4 EQU H'0004'
|
||||
PDC3 EQU H'0003'
|
||||
PDC2 EQU H'0002'
|
||||
PDC1 EQU H'0001'
|
||||
PDC0 EQU H'0000'
|
||||
|
||||
;----- ECCPAS Bits --------------------------------------------------------
|
||||
|
||||
ECCPASE EQU H'0007'
|
||||
ECCPAS2 EQU H'0006'
|
||||
ECCPAS1 EQU H'0005'
|
||||
ECCPAS0 EQU H'0004'
|
||||
PSSAC1 EQU H'0003'
|
||||
PSSAC0 EQU H'0002'
|
||||
PSSBD1 EQU H'0001'
|
||||
PSSBD0 EQU H'0000'
|
||||
|
||||
;----- WDTCON Bits --------------------------------------------------------
|
||||
|
||||
WDTPS3 EQU H'0004'
|
||||
WDTPS2 EQU H'0003'
|
||||
WDTPS1 EQU H'0002'
|
||||
WDTPS0 EQU H'0001'
|
||||
SWDTEN EQU H'0000'
|
||||
|
||||
;----- COMCON0 Bits -------------------------------------------------------
|
||||
|
||||
C2OUT EQU H'0007'
|
||||
C1OUT EQU H'0006'
|
||||
C2INV EQU H'0005'
|
||||
C1INV EQU H'0004'
|
||||
CIS EQU H'0003'
|
||||
CM2 EQU H'0002'
|
||||
CM1 EQU H'0001'
|
||||
CM0 EQU H'0000'
|
||||
|
||||
;----- COMCON1 Bits -------------------------------------------------------
|
||||
|
||||
T1GSS EQU H'0001'
|
||||
C2SYNC EQU H'0000'
|
||||
|
||||
;----- ADCON0 Bits --------------------------------------------------------
|
||||
|
||||
ADFM EQU H'0007'
|
||||
VCFG EQU H'0006'
|
||||
CHS2 EQU H'0004'
|
||||
CHS1 EQU H'0003'
|
||||
CHS0 EQU H'0002'
|
||||
GO EQU H'0001'
|
||||
NOT_DONE EQU H'0001'
|
||||
GO_DONE EQU H'0001'
|
||||
ADON EQU H'0000'
|
||||
|
||||
;----- OPTION Bits --------------------------------------------------------
|
||||
|
||||
NOT_RAPU EQU H'0007'
|
||||
INTEDG EQU H'0006'
|
||||
T0CS EQU H'0005'
|
||||
T0SE EQU H'0004'
|
||||
PSA EQU H'0003'
|
||||
PS2 EQU H'0002'
|
||||
PS1 EQU H'0001'
|
||||
PS0 EQU H'0000'
|
||||
|
||||
;----- PIE1 Bits ----------------------------------------------------------
|
||||
|
||||
EEIE EQU H'0007'
|
||||
ADIE EQU H'0006'
|
||||
CCP1IE EQU H'0005'
|
||||
C2IE EQU H'0004'
|
||||
C1IE EQU H'0003'
|
||||
OSFIE EQU H'0002'
|
||||
T2IE EQU H'0001'
|
||||
TMR2IE EQU H'0001'
|
||||
T1IE EQU H'0000'
|
||||
TMR1IE EQU H'0000'
|
||||
|
||||
;----- PCON Bits ----------------------------------------------------------
|
||||
|
||||
ULPWUE EQU H'0005'
|
||||
SBODEN EQU H'0004'
|
||||
NOT_POR EQU H'0001'
|
||||
NOT_BOD EQU H'0000'
|
||||
|
||||
;----- OSCCON Bits --------------------------------------------------------
|
||||
|
||||
IRCF2 EQU H'0006'
|
||||
IRCF1 EQU H'0005'
|
||||
IRCF0 EQU H'0004'
|
||||
OSTS EQU H'0003'
|
||||
HTS EQU H'0002'
|
||||
LTS EQU H'0001'
|
||||
SCS EQU H'0000'
|
||||
|
||||
;----- OSCTUNE Bits -------------------------------------------------------
|
||||
|
||||
TUN4 EQU H'0004'
|
||||
TUN3 EQU H'0003'
|
||||
TUN2 EQU H'0002'
|
||||
TUN1 EQU H'0001'
|
||||
TUN0 EQU H'0000'
|
||||
|
||||
;----- ANSEL --------------------------------------------------------------
|
||||
|
||||
ANS7 EQU H'0007'
|
||||
ANS6 EQU H'0006'
|
||||
ANS5 EQU H'0005'
|
||||
ANS4 EQU H'0004'
|
||||
ANS3 EQU H'0003'
|
||||
ANS2 EQU H'0002'
|
||||
ANS1 EQU H'0001'
|
||||
ANS0 EQU H'0000'
|
||||
|
||||
;----- IOC --------------------------------------------------------------
|
||||
|
||||
IOC5 EQU H'0005'
|
||||
IOC4 EQU H'0004'
|
||||
IOC3 EQU H'0003'
|
||||
IOC2 EQU H'0002'
|
||||
IOC1 EQU H'0001'
|
||||
IOC0 EQU H'0000'
|
||||
|
||||
;----- IOCA --------------------------------------------------------------
|
||||
|
||||
IOCA5 EQU H'0005'
|
||||
IOCA4 EQU H'0004'
|
||||
IOCA3 EQU H'0003'
|
||||
IOCA2 EQU H'0002'
|
||||
IOCA1 EQU H'0001'
|
||||
IOCA0 EQU H'0000'
|
||||
|
||||
;----- VRCON Bits ---------------------------------------------------------
|
||||
|
||||
VREN EQU H'0007'
|
||||
VRR EQU H'0005'
|
||||
VR3 EQU H'0003'
|
||||
VR2 EQU H'0002'
|
||||
VR1 EQU H'0001'
|
||||
VR0 EQU H'0000'
|
||||
|
||||
;----- EECON1 -------------------------------------------------------------
|
||||
|
||||
WRERR EQU H'0003'
|
||||
WREN EQU H'0002'
|
||||
WR EQU H'0001'
|
||||
RD EQU H'0000'
|
||||
|
||||
;----- ADCON1 -------------------------------------------------------------
|
||||
|
||||
ADCS2 EQU H'0006'
|
||||
ADCS1 EQU H'0005'
|
||||
ADCS0 EQU H'0004'
|
||||
|
||||
;==========================================================================
|
||||
;
|
||||
; RAM Definition
|
||||
;
|
||||
;==========================================================================
|
||||
|
||||
__MAXRAM H'FF'
|
||||
__BADRAM H'06', H'08'-H'09', H'0D', H'1B'-H'1D'
|
||||
__BADRAM H'86', H'88'-H'89', H'8D', H'93'-H'94', H'97'-H'98', H'C0'-H'EF'
|
||||
|
||||
;==========================================================================
|
||||
;
|
||||
; Configuration Bits
|
||||
;
|
||||
;==========================================================================
|
||||
|
||||
_FCMEN_ON EQU H'3FFF'
|
||||
_FCMEN_OFF EQU H'37FF'
|
||||
_IESO_ON EQU H'3FFF'
|
||||
_IESO_OFF EQU H'3BFF'
|
||||
_BOD_ON EQU H'3FFF'
|
||||
_BOD_NSLEEP EQU H'3EFF'
|
||||
_BOD_SBODEN EQU H'3DFF'
|
||||
_BOD_OFF EQU H'3CFF'
|
||||
_CPD_ON EQU H'3F7F'
|
||||
_CPD_OFF EQU H'3FFF'
|
||||
_CP_ON EQU H'3FBF'
|
||||
_CP_OFF EQU H'3FFF'
|
||||
_MCLRE_ON EQU H'3FFF'
|
||||
_MCLRE_OFF EQU H'3FDF'
|
||||
_PWRTE_OFF EQU H'3FFF'
|
||||
_PWRTE_ON EQU H'3FEF'
|
||||
_WDT_ON EQU H'3FFF'
|
||||
_WDT_OFF EQU H'3FF7'
|
||||
_LP_OSC EQU H'3FF8'
|
||||
_XT_OSC EQU H'3FF9'
|
||||
_HS_OSC EQU H'3FFA'
|
||||
_EC_OSC EQU H'3FFB'
|
||||
_INTRC_OSC_NOCLKOUT EQU H'3FFC'
|
||||
_INTRC_OSC_CLKOUT EQU H'3FFD'
|
||||
_EXTRC_OSC_NOCLKOUT EQU H'3FFE'
|
||||
_EXTRC_OSC_CLKOUT EQU H'3FFF'
|
||||
_INTOSCIO EQU H'3FFC'
|
||||
_INTOSC EQU H'3FFD'
|
||||
_EXTRCIO EQU H'3FFE'
|
||||
_EXTRC EQU H'3FFF'
|
||||
|
||||
LIST
|
||||
BIN
MainMotorDriver/MainMotorDriver.epb
Executable file
BIN
MainMotorDriver/MainMotorDriver.epb
Executable file
Binary file not shown.
BIN
MainMotorDriver/MainMotorDriver_Drv.epb
Executable file
BIN
MainMotorDriver/MainMotorDriver_Drv.epb
Executable file
Binary file not shown.
BIN
MainMotorDriver/MainMotorDriver_Drv2.epb
Executable file
BIN
MainMotorDriver/MainMotorDriver_Drv2.epb
Executable file
Binary file not shown.
BIN
MainMotorDriver/MainMotorDriver_OP.epb
Executable file
BIN
MainMotorDriver/MainMotorDriver_OP.epb
Executable file
Binary file not shown.
BIN
MainMotorDriver/Wingman MainMotorDriver.doc
Executable file
BIN
MainMotorDriver/Wingman MainMotorDriver.doc
Executable file
Binary file not shown.
BIN
MainMotorDriver/WingmanMainMotorDriver_Layout.pdf
Executable file
BIN
MainMotorDriver/WingmanMainMotorDriver_Layout.pdf
Executable file
Binary file not shown.
BIN
MainMotorDriver/WingmanMainMotorDriver_Schematic.pdf
Executable file
BIN
MainMotorDriver/WingmanMainMotorDriver_Schematic.pdf
Executable file
Binary file not shown.
BIN
MainMotorDriver/WingmanMainMotorDriver_Screen.pdf
Executable file
BIN
MainMotorDriver/WingmanMainMotorDriver_Screen.pdf
Executable file
Binary file not shown.
406
PPMDecoder/ASM/2313def.inc
Executable file
406
PPMDecoder/ASM/2313def.inc
Executable file
@ -0,0 +1,406 @@
|
||||
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
|
||||
;***** Created: 2005-01-11 10:30 ******* Source: AT90S2313.xml ***********
|
||||
;*************************************************************************
|
||||
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
|
||||
;*
|
||||
;* Number : AVR000
|
||||
;* File Name : "2313def.inc"
|
||||
;* Title : Register/Bit Definitions for the AT90S2313
|
||||
;* Date : 2005-01-11
|
||||
;* Version : 2.14
|
||||
;* Support E-mail : avr@atmel.com
|
||||
;* Target MCU : AT90S2313
|
||||
;*
|
||||
;* DESCRIPTION
|
||||
;* When including this file in the assembly program file, all I/O register
|
||||
;* names and I/O register bit names appearing in the data book can be used.
|
||||
;* In addition, the six registers forming the three data pointers X, Y and
|
||||
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
|
||||
;* SRAM is also defined
|
||||
;*
|
||||
;* The Register names are represented by their hexadecimal address.
|
||||
;*
|
||||
;* The Register Bit names are represented by their bit number (0-7).
|
||||
;*
|
||||
;* Please observe the difference in using the bit names with instructions
|
||||
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
|
||||
;* (skip if bit in register set/cleared). The following example illustrates
|
||||
;* this:
|
||||
;*
|
||||
;* in r16,PORTB ;read PORTB latch
|
||||
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
|
||||
;* out PORTB,r16 ;output to PORTB
|
||||
;*
|
||||
;* in r16,TIFR ;read the Timer Interrupt Flag Register
|
||||
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
|
||||
;* rjmp TOV0_is_set ;jump if set
|
||||
;* ... ;otherwise do something else
|
||||
;*************************************************************************
|
||||
|
||||
#ifndef _2313DEF_INC_
|
||||
#define _2313DEF_INC_
|
||||
|
||||
|
||||
#pragma partinc 0
|
||||
|
||||
; ***** SPECIFY DEVICE ***************************************************
|
||||
.device AT90S2313
|
||||
#pragma AVRPART ADMIN PART_NAME AT90S2313
|
||||
.equ SIGNATURE_000 = 0x1e
|
||||
.equ SIGNATURE_001 = 0x91
|
||||
.equ SIGNATURE_002 = 0x01
|
||||
|
||||
#pragma AVRPART CORE CORE_VERSION V1
|
||||
|
||||
|
||||
; ***** I/O REGISTER DEFINITIONS *****************************************
|
||||
; NOTE:
|
||||
; Definitions marked "MEMORY MAPPED"are extended I/O ports
|
||||
; and cannot be used with IN/OUT instructions
|
||||
.equ SREG = 0x3f
|
||||
.equ SPL = 0x3d
|
||||
.equ GIMSK = 0x3b
|
||||
.equ GIFR = 0x3a
|
||||
.equ TIMSK = 0x39
|
||||
.equ TIFR = 0x38
|
||||
.equ MCUCR = 0x35
|
||||
.equ TCCR0 = 0x33
|
||||
.equ TCNT0 = 0x32
|
||||
.equ TCCR1A = 0x2f
|
||||
.equ TCCR1B = 0x2e
|
||||
.equ TCNT1H = 0x2d
|
||||
.equ TCNT1L = 0x2c
|
||||
.equ OCR1AH = 0x2b
|
||||
.equ OCR1AL = 0x2a
|
||||
.equ ICR1H = 0x25
|
||||
.equ ICR1L = 0x24
|
||||
.equ WDTCR = 0x21
|
||||
.equ EEAR = 0x1e
|
||||
.equ EEDR = 0x1d
|
||||
.equ EECR = 0x1c
|
||||
.equ PORTB = 0x18
|
||||
.equ DDRB = 0x17
|
||||
.equ PINB = 0x16
|
||||
.equ PORTD = 0x12
|
||||
.equ DDRD = 0x11
|
||||
.equ PIND = 0x10
|
||||
.equ UDR = 0x0c
|
||||
.equ USR = 0x0b
|
||||
.equ UCR = 0x0a
|
||||
.equ UBRR = 0x09
|
||||
.equ ACSR = 0x08
|
||||
|
||||
|
||||
; ***** BIT DEFINITIONS **************************************************
|
||||
|
||||
; ***** PORTB ************************
|
||||
; PORTB - Port B Data Register
|
||||
.equ PORTB0 = 0 ; Port B Data Register bit 0
|
||||
.equ PB0 = 0 ; For compatibility
|
||||
.equ PORTB1 = 1 ; Port B Data Register bit 1
|
||||
.equ PB1 = 1 ; For compatibility
|
||||
.equ PORTB2 = 2 ; Port B Data Register bit 2
|
||||
.equ PB2 = 2 ; For compatibility
|
||||
.equ PORTB3 = 3 ; Port B Data Register bit 3
|
||||
.equ PB3 = 3 ; For compatibility
|
||||
.equ PORTB4 = 4 ; Port B Data Register bit 4
|
||||
.equ PB4 = 4 ; For compatibility
|
||||
.equ PORTB5 = 5 ; Port B Data Register bit 5
|
||||
.equ PB5 = 5 ; For compatibility
|
||||
.equ PORTB6 = 6 ; Port B Data Register bit 6
|
||||
.equ PB6 = 6 ; For compatibility
|
||||
.equ PORTB7 = 7 ; Port B Data Register bit 7
|
||||
.equ PB7 = 7 ; For compatibility
|
||||
|
||||
; DDRB - Port B Data Direction Register
|
||||
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
|
||||
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
|
||||
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
|
||||
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
|
||||
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
|
||||
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
|
||||
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
|
||||
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
|
||||
|
||||
; PINB - Port B Input Pins
|
||||
.equ PINB0 = 0 ; Port B Input Pins bit 0
|
||||
.equ PINB1 = 1 ; Port B Input Pins bit 1
|
||||
.equ PINB2 = 2 ; Port B Input Pins bit 2
|
||||
.equ PINB3 = 3 ; Port B Input Pins bit 3
|
||||
.equ PINB4 = 4 ; Port B Input Pins bit 4
|
||||
.equ PINB5 = 5 ; Port B Input Pins bit 5
|
||||
.equ PINB6 = 6 ; Port B Input Pins bit 6
|
||||
.equ PINB7 = 7 ; Port B Input Pins bit 7
|
||||
|
||||
|
||||
; ***** TIMER_COUNTER_0 **************
|
||||
; TIMSK - Timer/Counter Interrupt Mask Register
|
||||
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
; TIFR - Timer/Counter Interrupt Flag register
|
||||
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
|
||||
|
||||
; TCCR0 - Timer/Counter0 Control Register
|
||||
.equ CS00 = 0 ; Clock Select0 bit 0
|
||||
.equ CS01 = 1 ; Clock Select0 bit 1
|
||||
.equ CS02 = 2 ; Clock Select0 bit 2
|
||||
|
||||
; TCNT0 - Timer Counter 0
|
||||
.equ TCNT00 = 0 ; Timer Counter 0 bit 0
|
||||
.equ TCNT01 = 1 ; Timer Counter 0 bit 1
|
||||
.equ TCNT02 = 2 ; Timer Counter 0 bit 2
|
||||
.equ TCNT03 = 3 ; Timer Counter 0 bit 3
|
||||
.equ TCNT04 = 4 ; Timer Counter 0 bit 4
|
||||
.equ TCNT05 = 5 ; Timer Counter 0 bit 5
|
||||
.equ TCNT06 = 6 ; Timer Counter 0 bit 6
|
||||
.equ TCNT07 = 7 ; Timer Counter 0 bit 7
|
||||
|
||||
|
||||
; ***** TIMER_COUNTER_1 **************
|
||||
; TIMSK - Timer/Counter Interrupt Mask Register
|
||||
.equ TICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable
|
||||
.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable
|
||||
.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
; TIFR - Timer/Counter Interrupt Flag register
|
||||
.equ ICF1 = 3 ; Input Capture Flag 1
|
||||
.equ OCF1A = 6 ; Output Compare Flag 1A
|
||||
.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag
|
||||
|
||||
; TCCR1A - Timer/Counter1 Control Register A
|
||||
.equ PWM10 = 0 ; Pulse Width Modulator Select Bit 0
|
||||
.equ PWM11 = 1 ; Pulse Width Modulator Select Bit 1
|
||||
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0
|
||||
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
|
||||
|
||||
; TCCR1B - Timer/Counter1 Control Register B
|
||||
.equ CS10 = 0 ; Clock Select bit 0
|
||||
.equ CS11 = 1 ; Clock Select 1 bit 1
|
||||
.equ CS12 = 2 ; Clock Select1 bit 2
|
||||
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match
|
||||
.equ ICES1 = 6 ; Input Capture 1 Edge Select
|
||||
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
|
||||
|
||||
|
||||
; ***** WATCHDOG *********************
|
||||
; WDTCR - Watchdog Timer Control Register
|
||||
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
|
||||
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
|
||||
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
|
||||
.equ WDE = 3 ; Watch Dog Enable
|
||||
.equ WDTOE = 4 ; RW
|
||||
.equ WDDE = WDTOE ; For compatibility
|
||||
|
||||
|
||||
; ***** EXTERNAL_INTERRUPT ***********
|
||||
; GIMSK - General Interrupt Mask Register
|
||||
.equ INT0 = 6 ; External Interrupt Request 0 Enable
|
||||
.equ INT1 = 7 ; External Interrupt Request 1 Enable
|
||||
|
||||
; GIFR - General Interrupt Flag register
|
||||
.equ INTF0 = 6 ; External Interrupt Flag 0
|
||||
.equ INTF1 = 7 ; External Interrupt Flag 1
|
||||
|
||||
|
||||
; ***** UART *************************
|
||||
; UDR - UART I/O Data Register
|
||||
.equ UDR0 = 0 ; UART I/O Data Register bit 0
|
||||
.equ UDR1 = 1 ; UART I/O Data Register bit 1
|
||||
.equ UDR2 = 2 ; UART I/O Data Register bit 2
|
||||
.equ UDR3 = 3 ; UART I/O Data Register bit 3
|
||||
.equ UDR4 = 4 ; UART I/O Data Register bit 4
|
||||
.equ UDR5 = 5 ; UART I/O Data Register bit 5
|
||||
.equ UDR6 = 6 ; UART I/O Data Register bit 6
|
||||
.equ UDR7 = 7 ; UART I/O Data Register bit 7
|
||||
|
||||
; USR - UART Status Register
|
||||
.equ DOR = 3 ; Data overRun
|
||||
.equ FE = 4 ; Framing Error
|
||||
.equ UDRE = 5 ; UART Data Register Empty
|
||||
.equ TXC = 6 ; UART Transmit Complete
|
||||
.equ RXC = 7 ; UART Receive Complete
|
||||
|
||||
; UCR - UART Control Register
|
||||
.equ TXB8 = 0 ; Transmit Data Bit 8
|
||||
.equ RXB8 = 1 ; Receive Data Bit 8
|
||||
.equ CHR9 = 2 ; 9-bit Characters
|
||||
.equ TXEN = 3 ; Transmitter Enable
|
||||
.equ RXEN = 4 ; Receiver Enable
|
||||
.equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable
|
||||
.equ TXCIE = 6 ; TX Complete Interrupt Enable
|
||||
.equ RXCIE = 7 ; RX Complete Interrupt Enable
|
||||
|
||||
; UBRR - UART BAUD Rate Register
|
||||
.equ UBRR0 = 0 ; UART Baud Rate Register bit 0
|
||||
.equ UBRR1 = 1 ; UART Baud Rate Register bit 1
|
||||
.equ UBRR2 = 2 ; UART Baud Rate Register bit 2
|
||||
.equ UBRR3 = 3 ; UART Baud Rate Register bit 3
|
||||
.equ UBRR4 = 4 ; UART Baud Rate Register bit 4
|
||||
.equ UBRR5 = 5 ; UART Baud Rate Register bit 5
|
||||
.equ UBRR6 = 6 ; UART Baud Rate Register bit 6
|
||||
.equ UBRR7 = 7 ; UART Baud Rate Register bit 7
|
||||
|
||||
|
||||
; ***** ANALOG_COMPARATOR ************
|
||||
; ACSR - Analog Comparator Control And Status Register
|
||||
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
|
||||
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
|
||||
.equ ACIC = 2 ; Analog Comparator Input Capture Enable
|
||||
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
|
||||
.equ ACI = 4 ; Analog Comparator Interrupt Flag
|
||||
.equ ACO = 5 ; Analog Comparator Output
|
||||
.equ ACD = 7 ; Analog Comparator Disable
|
||||
|
||||
|
||||
; ***** CPU **************************
|
||||
; SREG - Status Register
|
||||
.equ SREG_C = 0 ; Carry Flag
|
||||
.equ SREG_Z = 1 ; Zero Flag
|
||||
.equ SREG_N = 2 ; Negative Flag
|
||||
.equ SREG_V = 3 ; Two's Complement Overflow Flag
|
||||
.equ SREG_S = 4 ; Sign Bit
|
||||
.equ SREG_H = 5 ; Half Carry Flag
|
||||
.equ SREG_T = 6 ; Bit Copy Storage
|
||||
.equ SREG_I = 7 ; Global Interrupt Enable
|
||||
|
||||
; SPL - Stack Pointer Low
|
||||
.equ SP0 = 0 ; Stack pointer bit 0
|
||||
.equ SP1 = 1 ; Stack pointer bit 1
|
||||
.equ SP2 = 2 ; Stack pointer bit 2
|
||||
.equ SP3 = 3 ; Stack pointer bit 3
|
||||
.equ SP4 = 4
|
||||
.equ SP5 = 5 ; Stack pointer bit 5
|
||||
.equ SP6 = 6 ; Stack pointer bit 6
|
||||
.equ SP7 = 7 ; Stack pointer bit 7
|
||||
|
||||
; MCUCR - MCU Control Register
|
||||
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
|
||||
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
|
||||
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0
|
||||
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1
|
||||
.equ SM = 4 ; Sleep Mode
|
||||
.equ SE = 5 ; Sleep Enable
|
||||
|
||||
|
||||
; ***** PORTD ************************
|
||||
; PORTD - Data Register, Port D
|
||||
.equ PORTD0 = 0 ;
|
||||
.equ PD0 = 0 ; For compatibility
|
||||
.equ PORTD1 = 1 ;
|
||||
.equ PD1 = 1 ; For compatibility
|
||||
.equ PORTD2 = 2 ;
|
||||
.equ PD2 = 2 ; For compatibility
|
||||
.equ PORTD3 = 3 ;
|
||||
.equ PD3 = 3 ; For compatibility
|
||||
.equ PORTD4 = 4 ;
|
||||
.equ PD4 = 4 ; For compatibility
|
||||
.equ PORTD5 = 5 ;
|
||||
.equ PD5 = 5 ; For compatibility
|
||||
.equ PORTD6 = 6 ;
|
||||
.equ PD6 = 6 ; For compatibility
|
||||
|
||||
; DDRD
|
||||
.equ DDD0 = 0 ;
|
||||
.equ DDD1 = 1 ;
|
||||
.equ DDD2 = 2 ;
|
||||
.equ DDD3 = 3 ;
|
||||
.equ DDD4 = 4 ;
|
||||
.equ DDD5 = 5 ;
|
||||
.equ DDD6 = 6 ;
|
||||
|
||||
; PIND - Input Pins, Port D
|
||||
.equ PIND0 = 0 ;
|
||||
.equ PIND1 = 1 ;
|
||||
.equ PIND2 = 2 ;
|
||||
.equ PIND3 = 3 ;
|
||||
.equ PIND4 = 4 ;
|
||||
.equ PIND5 = 5 ;
|
||||
.equ PIND6 = 6 ;
|
||||
|
||||
|
||||
; ***** EEPROM ***********************
|
||||
; EEAR - EEPROM Read/Write Access
|
||||
.equ EEARL = EEAR ; For compatibility
|
||||
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0
|
||||
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1
|
||||
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2
|
||||
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3
|
||||
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4
|
||||
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5
|
||||
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6
|
||||
|
||||
; EEDR - EEPROM Data Register
|
||||
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
|
||||
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
|
||||
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
|
||||
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
|
||||
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
|
||||
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
|
||||
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
|
||||
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
|
||||
|
||||
; EECR - EEPROM Control Register
|
||||
.equ EERE = 0 ; EEPROM Read Enable
|
||||
.equ EEWE = 1 ; EEPROM Write Enable
|
||||
.equ EEMWE = 2 ; EEPROM Master Write Enable
|
||||
|
||||
|
||||
|
||||
; ***** LOCKSBITS ********************************************************
|
||||
.equ LB1 = 0 ; Lockbit
|
||||
.equ LB2 = 1 ; Lockbit
|
||||
|
||||
|
||||
; ***** FUSES ************************************************************
|
||||
; LOW fuse bits
|
||||
|
||||
|
||||
|
||||
; ***** CPU REGISTER DEFINITIONS *****************************************
|
||||
.def XH = r27
|
||||
.def XL = r26
|
||||
.def YH = r29
|
||||
.def YL = r28
|
||||
.def ZH = r31
|
||||
.def ZL = r30
|
||||
|
||||
|
||||
|
||||
; ***** DATA MEMORY DECLARATIONS *****************************************
|
||||
.equ FLASHEND = 0x03ff ; Note: Word address
|
||||
.equ IOEND = 0x003f
|
||||
.equ SRAM_START = 0x0060
|
||||
.equ SRAM_SIZE = 128
|
||||
.equ RAMEND = 0x00df
|
||||
.equ XRAMEND = 0x0000
|
||||
.equ E2END = 0x007f
|
||||
.equ EEPROMEND = 0x007f
|
||||
.equ EEADRBITS = 7
|
||||
#pragma AVRPART MEMORY PROG_FLASH 2048
|
||||
#pragma AVRPART MEMORY EEPROM 128
|
||||
#pragma AVRPART MEMORY INT_SRAM SIZE 128
|
||||
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
; ***** INTERRUPT VECTORS ************************************************
|
||||
.equ INT0addr = 0x0001 ; External Interrupt Request 0
|
||||
.equ INT1addr = 0x0002 ; External Interrupt Request 1
|
||||
.equ ICP1addr = 0x0003 ; Timer/Counter1 Capture Event
|
||||
.equ OC1addr = 0x0004 ; Timer/Counter1 Compare Match
|
||||
.equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow
|
||||
.equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow
|
||||
.equ URXCaddr = 0x0007 ; UART, Rx Complete
|
||||
.equ UDREaddr = 0x0008 ; UART Data Register Empty
|
||||
.equ UTXCaddr = 0x0009 ; UART, Tx Complete
|
||||
.equ ACIaddr = 0x000a ; Analog Comparator
|
||||
|
||||
.equ INT_VECTORS_SIZE = 11 ; size in words
|
||||
|
||||
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
|
||||
|
||||
#endif /* _2313DEF_INC_ */
|
||||
|
||||
; ***** END OF FILE ******************************************************
|
||||
1
PPMDecoder/ASM/RCRXDecoder.aps
Executable file
1
PPMDecoder/ASM/RCRXDecoder.aps
Executable file
@ -0,0 +1 @@
|
||||
<AVRStudio><MANAGEMENT><ProjectName>RCRXDecoder</ProjectName><Created>10-Jan-2005 22:30:02</Created><LastEdit>21-Apr-2005 22:31:30</LastEdit><ICON>AVRAssembler.bmp</ICON><ProjectType>0</ProjectType><Created>10-Jan-2005 22:30:02</Created><Version>4</Version><Build>4, 10, 0,345</Build><ProjectTypeName>Atmel AVR Assembler</ProjectTypeName></MANAGEMENT><CODE_CREATION><ObjectFile>d:\-project-\rcrxdecoder\asm\rcrxdecoder.obj</ObjectFile><EntryFile>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</EntryFile><SaveFolder>D:\-Project-\RCRXDecoder\ASM\</SaveFolder></CODE_CREATION><DEBUG_TARGET><CURRENT_TARGET>ICE200</CURRENT_TARGET><CURRENT_PART>AT90S2313</CURRENT_PART><BREAKPOINTS></BREAKPOINTS><IO_EXPAND><Item>256</Item><Item>230</Item><Item>17</Item><Item>0</Item><Item>80</Item><Item>81</Item><Item>83</Item><Item>85</Item><Item>99</Item><Item>103</Item><Item>107</Item><Item>112</Item><Item>173</Item><Item>174</Item><Item>180</Item><Item>181</Item><Item>184</Item><Item>187</Item><Item>197</Item><Item>203</Item><Item>221</Item><Item>222</Item><Item>231</Item><Item>249</Item><Item>299</Item><Item>256</Item><Item>17</Item><Item>180</Item><Item>173</Item><Item>17</Item><Item>230</Item><Item>231</Item><Item>17</Item><Item>256</Item><Item>17</Item><Item>17</Item><Item>256</Item><Item>17</Item><Item>51</Item><HIDE>false</HIDE></IO_EXPAND><REGISTERNAMES><Register>R00</Register><Register>R01</Register><Register>R02</Register><Register>R03</Register><Register>R04</Register><Register>R05</Register><Register>R06</Register><Register>R07</Register><Register>R08</Register><Register>R09</Register><Register>R10</Register><Register>R11</Register><Register>R12</Register><Register>R13</Register><Register>R14</Register><Register>R15</Register><Register>R16</Register><Register>R17</Register><Register>R18</Register><Register>R19</Register><Register>R20</Register><Register>R21</Register><Register>R22</Register><Register>R23</Register><Register>R24</Register><Register>R25</Register><Register>R26</Register><Register>R27</Register><Register>R28</Register><Register>R29</Register><Register>R30</Register><Register>R31</Register></REGISTERNAMES><COM>COM1</COM><COMType>1</COMType><WATCHNUM>0</WATCHNUM><WATCHNAMES><Pane0></Pane0><Pane1></Pane1><Pane2></Pane2><Pane3></Pane3></WATCHNAMES><BreakOnTrcaeFull>0</BreakOnTrcaeFull></DEBUG_TARGET><FilesInProject><Assembler><OpenString>Assembler File (*.asm)|*.asm;|AllFiles(*.*)|*.*|</OpenString></Assembler></FilesInProject><ICE200><Settings>1</Settings><Options>5</Options><Use115200>1</Use115200><emConfig>27</emConfig></ICE200><ProjectIncludeDirs><Dirs><Dir>C:\Program Files\Atmel\AVR Tools\AvrAssembler2\Appnotes</Dir></Dirs></ProjectIncludeDirs><Files><File00000><FileId>00000</FileId><Path>D:\-Project-\RCRXDecoder\ASM\</Path><Name>RCRXDecoder.map</Name><Status>96</Status></File00000><File00001><FileId>00001</FileId><Path>D:\-Project-\RCRXDecoder\ASM\</Path><Name>2313def.inc</Name><Status>257</Status></File00001><File00002><FileId>00002</FileId><Path>D:\-Project-\RCRXDecoder\ASM\</Path><Name>tn2313def.inc</Name><Status>1</Status></File00002><File00003><FileId>00003</FileId><Path>D:\-Project-\RCRXDecoder\ASM\</Path><Name>RCRXDecoder.asm</Name><Status>263</Status></File00003><File00004><FileId>00004</FileId><Path>D:\-Project-\RCRXDecoder\ASM\</Path><Name>RCRXDecoder.map</Name><Status>96</Status></File00004><File00005><FileId>00005</FileId><Path>D:\-Project-\RCRXDecoder\ASM\</Path><Name>RCRXDecoder.map</Name><Status>96</Status></File00005><File00006><FileId>00006</FileId><Path>D:\-Project-\RCRXDecoder\ASM\</Path><Name>RCRXDecoder.map</Name><Status>96</Status></File00006><File00007><FileId>00007</FileId><Path>D:\-Project-\RCRXDecoder\ASM\</Path><Name>RCRXDecoder.map</Name><Status>96</Status></File00007><File00008><FileId>00008</FileId><Path>D:\-Project-\RCRXDecoder\ASM\</Path><Name>RCRXDecoder.map</Name><Status>96</Status></File00008></Files><Workspace><File00001><Position>-687 87 123 493</Position><LineCol>0 0</LineCol></File00001><File00002><Position>-665 109 145 515</Position><LineCol>0 0</LineCol></File00002><File00003><Position>4 83 1020 688</Position><LineCol>111 0</LineCol><State>Maximized</State></File00003></Workspace><Events><Breakpoints></Breakpoints><Tracepoints><File00003></File00003></Tracepoints><Bookmarks></Bookmarks></Events><Trace><Filters></Filters></Trace></AVRStudio>
|
||||
666
PPMDecoder/ASM/RCRXDecoder.asm
Executable file
666
PPMDecoder/ASM/RCRXDecoder.asm
Executable file
@ -0,0 +1,666 @@
|
||||
;==========================================================================================================
|
||||
;
|
||||
; CMtec RCRXDecoder copyright 2005 v1.0 (2005-01-23)
|
||||
;
|
||||
; Name: Christoffer Martinsson
|
||||
; E-mail: cm@wsm.se
|
||||
;
|
||||
; 7ch PPM decoder for RC-Receivers.
|
||||
; Based on Atmel AT90S2313 or ATTiny2313 with 10 or 20Mhz crystal.
|
||||
;
|
||||
; This DSP is build on the idea of having one inputDecoding and one outputEncoding working simultanius.
|
||||
; This to manage decode seven (or more) channels and not to be bound to use the "spare"-time at the end
|
||||
; of the pulseFrame.
|
||||
;
|
||||
; PORTB,PB0-PB7 assign to output ch 1 to ch 7 (ch 8 reserved)
|
||||
; PORTD,PD2 assign to input PPM-signal from RX
|
||||
; PORTD,PD3 assign to StoreButton/Jumper
|
||||
; PORTD,PD4 assign to red LED
|
||||
; PORTD,PD5 assign to yellow LED
|
||||
;
|
||||
; The inputsignal is decoded into two separate buffert locations in the SRAM. The output-routine work
|
||||
; with the buffert that the input-routine NOT currently working with. After a "good" frame is decoded,
|
||||
; the buffertPointer is switched. This to ensure that a "good" pulseframe allways is available if a error
|
||||
; should occur.
|
||||
;
|
||||
;
|
||||
; * Up to 8 channels
|
||||
; * 100step/ms resolution at 10Mhz, 200step/ms resolution at 20Mhz
|
||||
; * Allways a "good" output-signal
|
||||
; * Output is "Freezed" if error occurs
|
||||
; * Failsafe sets predefined values if error not recovered in (recomended) 2sec (max 8sec/10Mhz, 4sec/20Mhz)
|
||||
; * Failsafe-value easily changed by pressing a button
|
||||
; * PulseValue filtered to a smooth average-value
|
||||
; * Error/Glitch indicator
|
||||
;
|
||||
;==========================================================================================================
|
||||
; Processor-type
|
||||
.EQU AT90S2313 = 1
|
||||
;.EQU ATTiny2313 = 1
|
||||
|
||||
.NOLIST ; Disable listfile generation
|
||||
.ifdef AT90S2313
|
||||
.INCLUDE "2313def.inc"
|
||||
.else
|
||||
.INCLUDE "tn2313def.inc"
|
||||
.endif
|
||||
.LIST ; Reenable listfile generation
|
||||
|
||||
; General definitions
|
||||
; Adjust this numbers to make it work propely with your application
|
||||
|
||||
.EQU XTAL =10 ; Used crystal (Mhz) (min 10Mhz)
|
||||
.EQU RecoveryNr =1 ; Number of "good" pulseFrames to recover from error-state
|
||||
.EQU NrOfChannels =7 ; Numbers of channels (max 8)
|
||||
.EQU FailSafeTime =2 ; Time before enter failsafe (sec) (max 8sec/10Mhz, 4sec/20Mhz)
|
||||
|
||||
; 8bit register
|
||||
.DEF temp =r16 ; Temporary register
|
||||
.DEF nextSRAMAddress =r12 ; Register for storing secondary SRAMAddress (buffert2)
|
||||
.DEF debounceFilter =r15 ; Button-debounce register
|
||||
.DEF timeout =r17 ; Timeout counter
|
||||
.DEF chAddressEE =r18 ; EEPROM channelAddress
|
||||
.DEF chAddressIn =r19 ; Input channelAddress
|
||||
.DEF chAddressOut =r20 ; Output channelAddress
|
||||
.DEF chAddressFS =r21 ; Failsafe channelAddress
|
||||
.DEF pulseError =r22 ; PulseErrorCounter
|
||||
.DEF pulseFlag =r23 ; Flag register
|
||||
|
||||
; "16bit" register
|
||||
.DEF frameCalcL =r13 ; Register for calculate FrameTime
|
||||
.DEF frameCalcH =r14
|
||||
.DEF tempL =r24 ; Temporary register
|
||||
.DEF tempH =r25
|
||||
.DEF pulseInL =r26 ; InputPulseCounter
|
||||
.DEF pulseInH =r27
|
||||
.DEF pulseOutL =r28 ; OutputPulseCounter
|
||||
.DEF pulseOutH =r29
|
||||
|
||||
; pulseFlag bit-definitions
|
||||
.EQU SYNC =0 ; Sync found-Flag
|
||||
.EQU LEDredActive =1 ; LEDred Active-Flag
|
||||
.EQU LEDyellowActive =2 ; LEDyellow Active-Flag
|
||||
.EQU BuffertToUse =3 ; Buffert-Flag (0=buffert1, 1=buffert2)
|
||||
|
||||
; Output bit-definitions
|
||||
.EQU PPMSignal =2 ; PD2 Input for PPM-signal
|
||||
.EQU StoreButton =3 ; PD3 Input for StoreButton
|
||||
.EQU LEDred =4 ; PD4 Output for LEDred
|
||||
.EQU LEDyellow =5 ; PD5 Output for LEDyellow
|
||||
|
||||
; Memory definitions
|
||||
.EQU SRAMaddress1 =0x0060 ; Startlocation for buffert1 in SRAM
|
||||
.EQU SRAMAddress2 =0x0074 ; Startlocation for buffert2 in SRAM
|
||||
.EQU EEPROMaddress =0x0000 ; Startlocation for failsafe-storage in EEPROM
|
||||
|
||||
; Time definitions (timer0)
|
||||
.EQU FSTimeoutTime =(2*XTAL*FailSafeTime) ; 1sec*FailSafeTime
|
||||
|
||||
; Time definitions (timer1)
|
||||
.EQU MinPulseTime =(95*(XTAL/10)) ; ~0,95ms
|
||||
.EQU MaxPulseTime =(220*(XTAL/10)) ; ~2,2ms
|
||||
.EQU MinSyncTime =(400*(XTAL/10)) ; ~4ms
|
||||
.EQU MaxSyncTime =(1400*(XTAL/10)) ; ~14ms
|
||||
.EQU FrameTime =(1950*(XTAL/10)) ; ~20ms
|
||||
|
||||
.CSEG ; CODE segment
|
||||
.ORG 0
|
||||
;==========================================================================================================
|
||||
; Reset- and Interrupt-vectors
|
||||
;==========================================================================================================
|
||||
RJMP Main ; Reset Handler
|
||||
RJMP Ex_Int0 ; External Interrupt0 Handler
|
||||
RETI ; External Interrupt1 Handler
|
||||
RETI ; Timer1 Capture Handler
|
||||
RJMP Timer_Int1 ; Timer1 CompareA Handler
|
||||
RETI ; Timer1 Overflow Handler
|
||||
RJMP Timer_Int0 ; Timer0 Overflow Handler
|
||||
RETI ; USART0 RX Complete Handler
|
||||
RETI ; USART0,UDR Empty Handler
|
||||
RETI ; USART0 TX Complete Handler
|
||||
RETI ; Analog Comparator Handler
|
||||
|
||||
.ifdef ATTiny2313
|
||||
|
||||
RETI ; Pin Change Interrupt
|
||||
RETI ; Timer1 Compare B Handler
|
||||
RETI ; Timer0 Compare A Handler
|
||||
RETI ; Timer0 Compare B Handler
|
||||
RETI ; USI Start Handler
|
||||
RETI ; USI Overflow Handler
|
||||
RETI ; EEPROM Ready Handler
|
||||
RETI ; Watchdog Overflow Handler
|
||||
.endif
|
||||
;==========================================================================================================
|
||||
; Macro
|
||||
;==========================================================================================================
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Load16Temp
|
||||
;
|
||||
; Description: Load 16bit tempReg with 16bit @0-value
|
||||
;
|
||||
; Input: @0,@1
|
||||
; ChangedReg: tempH,tempL
|
||||
; UsedReg: tempH,tempL
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO Load16Temp
|
||||
LDI tempH,HIGH(@0)
|
||||
LDI tempL,LOW(@0)
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Compare16Temp
|
||||
;
|
||||
; Description: Compare 16bit tempReg with 16bit @0,@1-reg
|
||||
;
|
||||
; Input: @0,@1
|
||||
; ChangedReg: Carry
|
||||
; UsedReg: tempH,tempL
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO Compare16Temp
|
||||
CP tempL,@1
|
||||
CPC tempH,@0
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Clear16Reg
|
||||
;
|
||||
; Description: Clear 16bit @0,@1-register
|
||||
;
|
||||
; Input: @0,@1
|
||||
; ChangedReg: @0,@1
|
||||
; UsedReg: -
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO Clear16Reg
|
||||
CLR @0
|
||||
CLR @1
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Add16Reg
|
||||
;
|
||||
; Description: Add 16bit @2,@3 to 16bit @0,@1
|
||||
;
|
||||
; Input: @0,@1
|
||||
; ChangedReg: @0,@1,Carry
|
||||
; UsedReg: -
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO Add16Reg
|
||||
ADD @1,@3
|
||||
ADC @0,@2
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Sub16Reg
|
||||
;
|
||||
; Description: Subtract 16bit @2,@3 from 16bit @0,@1
|
||||
;
|
||||
; Input: @0,@1
|
||||
; ChangedReg: @0,@1,Carry
|
||||
; UsedReg: -
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO Sub16Reg
|
||||
SUB @1,@3
|
||||
SBC @0,@2
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; DivByTwo16Reg
|
||||
;
|
||||
; Description: Divide 16bit @0,@1 by two
|
||||
;
|
||||
; Input: @0,@1
|
||||
; ChangedReg: @0,@1
|
||||
; UsedReg: -
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO DivByTwo16Reg
|
||||
CLC
|
||||
ROR @0
|
||||
ROR @1
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Write16SRAM
|
||||
;
|
||||
; Description: Write data in 16bit @1,@2-reg to SRAM at position @0
|
||||
;
|
||||
; (BuffertToUse-Flag: 0=buffert1, 1=buffert2)
|
||||
;
|
||||
; Input: @0,@1,@2
|
||||
; ChangedReg: -
|
||||
; UsedReg: ZL,pulseFlag
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO Write16SRAM
|
||||
LDI ZL,LOW(SRAMaddress1)
|
||||
SBRC pulseFlag,BuffertToUse
|
||||
ADD ZL,nextSRAMAddress
|
||||
ADD ZL,@0
|
||||
ST Z+,@1
|
||||
ST Z,@2
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Read16SRAM
|
||||
;
|
||||
; Description: Read data in SRAM at position @0 to 16bir @1,@2-reg
|
||||
;
|
||||
; (BuffertToUse-Flag: 0=buffert1, 1=buffert2)
|
||||
;
|
||||
; Input: @0,@1,@2
|
||||
; ChangedReg: @1,@2
|
||||
; UsedReg: ZL,pulseFlag
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO Read16SRAM
|
||||
LDI ZL,LOW(SRAMaddress1)
|
||||
SBRC pulseFlag,BuffertToUse
|
||||
ADD ZL,nextSRAMAddress
|
||||
ADD ZL,@0
|
||||
LD @1,Z+
|
||||
LD @2,Z
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Write16EEPROM
|
||||
;
|
||||
; Description: Write data in 16bit @1,@2-reg to EEPROM at position @0
|
||||
;
|
||||
; Input: @0,@1,@2
|
||||
; ChangedReg: -
|
||||
; UsedReg: temp,EECR,EEARL,EEDR
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO Write16EEPROM
|
||||
MWEEWait1: SBIC EECR,1
|
||||
RJMP MWEEWait1
|
||||
LDI temp,LOW(EEPROMaddress)
|
||||
ADD temp,@0
|
||||
OUT EEARL,temp
|
||||
OUT EEDR,@1
|
||||
SBI EECR,EEMWE
|
||||
SBI EECR,EEWE
|
||||
|
||||
MWEEWait2: SBIC EECR,1
|
||||
RJMP MWEEWait2
|
||||
LDI temp,LOW(EEPROMaddress)
|
||||
ADD temp,@0
|
||||
INC temp
|
||||
OUT EEARL,temp
|
||||
OUT EEDR,@2
|
||||
SBI EECR,EEMWE
|
||||
SBI EECR,EEWE
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Read16EEPROM
|
||||
;
|
||||
; Description: Read data in EEPROM at position @0 to 16bir @1,@2-reg
|
||||
;
|
||||
; Input: @0,@1,@2
|
||||
; ChangedReg: @1,@2
|
||||
; UsedReg: temp,EECR,EEARL,EEDR
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO Read16EEPROM
|
||||
MREEWait1: SBIC EECR,1
|
||||
RJMP MREEWait1
|
||||
LDI temp,LOW(EEPROMaddress)
|
||||
ADD temp,@0
|
||||
OUT EEARL,temp
|
||||
SBI EECR,EERE
|
||||
IN @1,EEDR
|
||||
|
||||
MREEWait2: SBIC EECR,1
|
||||
RJMP MREEWait2
|
||||
LDI temp,LOW(EEPROMaddress)
|
||||
ADD temp,@0
|
||||
INC temp
|
||||
OUT EEARL,temp
|
||||
SBI EECR,EERE
|
||||
IN @2,EEDR
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; StartTimer0
|
||||
;
|
||||
; Description: Start timer0. Prescale set to CK/1024
|
||||
;
|
||||
; Input: -
|
||||
; ChangedReg: -
|
||||
; UsedReg: temp,TCCR0
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO StartTimer0
|
||||
LDI temp,0x05
|
||||
OUT TCCR0,temp ; Prescale set to CK/1024
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; StopTimer0
|
||||
;
|
||||
; Description: Stop timer0
|
||||
;
|
||||
; Input: -
|
||||
; ChangedReg: -
|
||||
; UsedReg: temp,TCCR0
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO StopTimer0
|
||||
CLR temp
|
||||
OUT TCCR0,temp
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; StartTimer1
|
||||
;
|
||||
; Description: Star timer1. Prescale set to CK
|
||||
;
|
||||
; Input: -
|
||||
; ChangedReg: -
|
||||
; UsedReg: temp,OCR1AH,OCR1AL,TCCR1B
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO StartTimer1
|
||||
LDI temp,HIGH(100)
|
||||
OUT OCR1AH,temp
|
||||
LDI temp,LOW(100)
|
||||
OUT OCR1AL,temp
|
||||
LDI temp,0x09
|
||||
OUT TCCR1B,temp ; Prescale set to CK
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; StopTimer1
|
||||
;
|
||||
; Description: Stop timer1
|
||||
;
|
||||
; Input: -
|
||||
; ChangedReg: -
|
||||
; UsedReg: temp,TCCR1B
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO StopTimer1
|
||||
CLR temp
|
||||
OUT TCCR1B,temp
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; StoreTempOnStack
|
||||
;
|
||||
; Description: Store Status and temp-register on Stack
|
||||
;
|
||||
; Input: -
|
||||
; ChangedReg: -
|
||||
; UsedReg: temp,tempH,tempL,SREG
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO StoreTempOnStack
|
||||
PUSH tempH
|
||||
PUSH tempL
|
||||
PUSH temp
|
||||
IN temp,SREG
|
||||
PUSH temp
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; RestoreTempFromStack
|
||||
;
|
||||
; Description: Restore Status and temp-register from Stack
|
||||
;
|
||||
; Input: -
|
||||
; ChangedReg: temp,tempH,tempL,SREG
|
||||
; UsedReg: temp,tempH,tempL,SREG
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO RestoreTempFromStack
|
||||
POP temp
|
||||
OUT SREG,temp
|
||||
POP temp
|
||||
POP tempL
|
||||
POP tempH
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; SwitchBuffert
|
||||
;
|
||||
; Description: Switches buffertPointer in SRAM (BuffertToUse-Flag: 0=buffert1, 1=buffert2)
|
||||
;
|
||||
; Input: -
|
||||
; ChangedReg: pulseFlag
|
||||
; UsedReg: temp,pulseFlag
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO SwitchBuffert
|
||||
LDI temp,(1<<BuffertToUse)
|
||||
EOR pulseFlag,temp ; Switch Buffert in SRAM
|
||||
.ENDMACRO
|
||||
;==========================================================================================================
|
||||
; Interrupt routines
|
||||
;==========================================================================================================
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Ex_Int0
|
||||
;
|
||||
; Description: Measure incoming pulse-value, filter it and then store it in SRAM.
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
Ex_Int0: StoreTempOnStack
|
||||
|
||||
ChkSync: SBRC pulseFlag,SYNC ; Check if sync found
|
||||
RJMP ChkError
|
||||
Load16Temp MinSyncTime
|
||||
Compare16Temp pulseInH,pulseInL ; Check if pulseIn > MinSyncTime
|
||||
BRCC Error; ; If not then jump to Error
|
||||
Load16Temp MaxSyncTime
|
||||
Compare16Temp pulseInH,pulseInL ; Check if pulseIn < MaxSyncTime
|
||||
BRCS Error ; If not then jump to Error
|
||||
SBR pulseFlag,(1<<SYNC) ; SYNC-Flag set
|
||||
CLR chAddressIn ; Clear chAddressIn
|
||||
|
||||
ChkSyncExit:Clear16Reg pulseInH,pulseInL ; Clear pulseIn register
|
||||
RestoreTempFromStack
|
||||
RETI
|
||||
|
||||
ChkError: Load16Temp MinPulseTime
|
||||
Compare16Temp pulseInH,pulseInL ; Check if pulseIn > MinPulseTime
|
||||
BRCC Error ; If not then jump to Error
|
||||
Load16Temp MaxPulseTime
|
||||
Compare16Temp pulseInH,pulseInL ; Check if pulseIn < MaxPulseTime
|
||||
BRCS Error ; If not then jump to Error
|
||||
|
||||
CPI pulseError,0 ; Check if pulseError == 0
|
||||
BREQ NoError ; If true then jump to NoError
|
||||
DEC pulseError ; Decrement pulseError
|
||||
|
||||
INC chAddressIn ; Increment pulseOut-address twice
|
||||
INC chAddressIn
|
||||
CPI chAddressIn,(NrOfChannels*2) ; Check if chAddress == (NrOfChannels*2)
|
||||
BRNE ChkErrExit ; If not then jump to ChkErrExit
|
||||
CBR pulseFlag,(1<<SYNC) ; Clear SYNC-Flag
|
||||
Clear16Reg frameCalcH,frameCalcL ; Clear FrameCalculation register
|
||||
|
||||
ChkErrExit: Clear16Reg pulseInH,pulseInL ; Clear pulseIn register
|
||||
RestoreTempFromStack
|
||||
RETI
|
||||
|
||||
Error: CBR pulseFlag,(1<<SYNC) ; SYNC-Flagg cleared
|
||||
SBR pulseFlag,(1<<LEDredActive) ; LEDActive-Flag set
|
||||
LDI pulseError,(RecoveryNr*NrOfChannels); pulseError = (RecoveryNr*NrOfChannels)
|
||||
|
||||
ErrorExit: Clear16Reg pulseInH,pulseInL ; Clear pulseIn register
|
||||
RestoreTempFromStack
|
||||
RETI
|
||||
|
||||
NoError: CLR timeout ; Clear timeout register
|
||||
CLR chAddressFS ; Clear chAddressEE
|
||||
StartTimer0 ; Start timer0
|
||||
|
||||
Read16SRAM chAddressIn,tempH,tempL ; Copy SRAM to temp
|
||||
Add16Reg pulseInH,pulseInL,tempH,tempL ; Add past value to current value
|
||||
DivByTwo16Reg pulseInH,pulseInL ; Divide value by two
|
||||
|
||||
Write16SRAM chAddressIn,pulseInH,pulseInL ; Copy temp to SRAM
|
||||
Add16Reg frameCalcH,frameCalcL,pulseInH,pulseInL; Add curren value to frameCalc register
|
||||
|
||||
INC chAddressIn ; Increment pulseOut-address twice
|
||||
INC chAddressIn
|
||||
CPI chAddressIn,(NrOfChannels*2) ; Check if chAddress == (NrOfChannels*2)
|
||||
BRNE NoErrorExit ; If not then jump to NoErrorExit
|
||||
CBR pulseFlag,(1<<SYNC) ; Clear SYNC-Flag
|
||||
|
||||
Load16Temp FrameTime
|
||||
Sub16Reg tempH,tempL,frameCalcH,frameCalcL ; Calculate frame-time
|
||||
Write16SRAM chAddressIn,tempH,tempL ; Write frame-time to SRAM
|
||||
|
||||
SwitchBuffert ; Switch Buffert in SRAM
|
||||
CBR pulseFlag,(1<<LEDredActive) ; LEDredActive-Flag cleared
|
||||
CBR pulseFlag,(1<<LEDyellowActive) ; LEDywllowActive-Flag cleared
|
||||
|
||||
Clear16Reg frameCalcH,frameCalcL ; Clear frameCalc register
|
||||
|
||||
NoErrorExit:Clear16Reg pulseInH,pulseInL ; Clear pulseIn register
|
||||
RestoreTempFromStack
|
||||
RETI
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Timer_Int1
|
||||
;
|
||||
; Description: Generate output-pulses from SRAM to PORTB. Increment pulseIn and pulseOut counter-registers
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
Timer_Int1: StoreTempOnStack
|
||||
|
||||
ADIW pulseInL,1 ; Increment pulseIn register
|
||||
ADIW pulseOutL,1 ; Increment pulseOut register
|
||||
CPI chAddressOut,0 ; Check if chAddressOut == 0
|
||||
BRNE ReadOPulse ; If true then jump to ReadOPulse
|
||||
LDI temp,0x01
|
||||
OUT PORTB,temp ; PORTB = 0x01
|
||||
|
||||
ReadOPulse: SwitchBuffert ; Switch Buffert in SRAM
|
||||
Read16SRAM chAddressOut,tempH,tempL ; Copy SRAM to temp
|
||||
SwitchBuffert ; Switch Buffert in SRAM
|
||||
Compare16Temp pulseOutH,pulseOutL ; Check if pulseOut < temp
|
||||
BRCS NextOPulse ; If not then jump to NextOPulse
|
||||
RestoreTempFromStack
|
||||
RETI
|
||||
|
||||
NextOPulse: CPI chAddressOut,(NrOfChannels*2) ; Check if chAddressOut ==
|
||||
BREQ ResetOPulse ; (NrOfChannels*2)
|
||||
IN temp,PORTB ; If true then jump to ResetOPulse
|
||||
LSL temp
|
||||
OUT PORTB,temp ; Roll PORTB left
|
||||
INC chAddressOut ; Increment chAddressOut twice
|
||||
INC chAddressOut
|
||||
Clear16Reg pulseOutH,pulseOutL ; Clear pulseOut register
|
||||
RestoreTempFromStack
|
||||
RETI
|
||||
|
||||
ResetOPulse:CLR chAddressOut ; Clear chAddressOut register
|
||||
Clear16Reg pulseOutH,pulseOutL ; Clear pulseOut register
|
||||
RestoreTempFromStack
|
||||
RETI
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Timer_Int0
|
||||
;
|
||||
; Description: Failsafe "watchdog". Restore pulse-value from EEPROM to SRAM if timeout occurs.
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
Timer_Int0: StoreTempOnStack
|
||||
CPI timeout,FStimeoutTime ; Check if timeout == FailsafeTime
|
||||
BREQ CopyPulseES ; If true then jump to CopyPulseES
|
||||
INC timeout ; Increment timeout
|
||||
RestoreTempFromStack
|
||||
RETI
|
||||
|
||||
CopyPulseES:SBR pulseFlag,(1<<LEDyellowActive) ; LEDActive-Flgg set
|
||||
Read16EEPROM chAddressFS,tempH,tempL ; Copy EEPROM to temp
|
||||
Write16SRAM chAddressFS,tempH,tempL ; Copy temp to SRAM
|
||||
SwitchBuffert ; Switch Buffert in SRAM
|
||||
Write16SRAM chAddressFS,tempH,tempL ; Copy temp to SRAM
|
||||
SwitchBuffert ; Switch Buffert in SRAM
|
||||
INC chAddressFS ; Increment chAddressFS twice
|
||||
INC chAddressFS
|
||||
CPI chAddressFS,((NrOfChannels*2)+2) ; Check if chAddressFS == ((NrOfChannels*2)+2)
|
||||
BRNE NextPulseES ; If not true then jump to NextPulseES
|
||||
StopTimer0 ; Stop timer0
|
||||
|
||||
NextPulseES:RestoreTempFromStack
|
||||
RETI
|
||||
|
||||
;==========================================================================================================
|
||||
; Main
|
||||
;==========================================================================================================
|
||||
Main: LDI temp,LOW(RAMEND)
|
||||
OUT SPL,temp ; Set StackPointeradress
|
||||
|
||||
CLI ; Disable GlobalInterrupt
|
||||
|
||||
;Init I/O
|
||||
LDI temp,0xFF
|
||||
OUT DDRB,temp ; All output on PORTB
|
||||
SBI DDRD,LEDred ; All input except PIN"LEDred"
|
||||
SBI DDRD,LEDyellow ; and PIN"LEDyellow"
|
||||
SBI PORTD,PPMSignal ; Enable pullup on INT0 input
|
||||
SBI PORTD,StoreButton ; Enable pullup on StoreButton input
|
||||
|
||||
LDI temp,(1<<INT0)
|
||||
OUT GIMSK,temp ; Enable external interrupt 0
|
||||
LDI temp,(1<<ISC01)
|
||||
OUT MCUCR,temp ; Trigg on falling edge
|
||||
LDI temp,(1<<OCIE1A)|(1<<TOIE0)
|
||||
OUT TIMSK,temp ; Enable internal timer0
|
||||
; and timer1 interrupt
|
||||
;Reset register
|
||||
CLR chAddressOut
|
||||
CLR chAddressIn
|
||||
CLR chAddressFS
|
||||
CLR chAddressEE
|
||||
CLR timeout
|
||||
CLR pulseFlag
|
||||
CLR ZH ; Clear Z-Pointer MSB
|
||||
Clear16Reg pulseInH,pulseInL ; Clear pulseIn-Reg
|
||||
Clear16Reg pulseOutH,pulseOutL ; Clear pulseOut-Reg
|
||||
|
||||
LDI temp,(LOW(SRAMAddress2)-SRAMAddress1)
|
||||
MOV nextSRAMAddress,temp ; Set nextSRAMAddress
|
||||
|
||||
InitMemES: Read16EEPROM chAddressEE,tempH,tempL ; Copy pulse-value from EEPROM to SRAM
|
||||
Write16SRAM chAddressEE,tempH,tempL
|
||||
SwitchBuffert ; Switch Buffert in SRAM
|
||||
Write16SRAM chAddressEE,tempH,tempL
|
||||
SwitchBuffert ; Switch Buffert in SRAM
|
||||
INC chAddressEE
|
||||
INC chAddressEE
|
||||
CPI chAddressEE,((NrOfChannels*2)+2);
|
||||
BRNE InitMemES
|
||||
|
||||
CBR pulseFlag,(1<<SYNC) ; Generate error
|
||||
SBR pulseFlag,(1<<LEDredActive)
|
||||
LDI pulseError,(RecoveryNr*NrOfChannels)
|
||||
|
||||
SEI ; Enable GlobalInterrupt
|
||||
|
||||
|
||||
;Start Timers
|
||||
StartTimer1 ; Start timer1
|
||||
StartTimer0 ; Start timer0
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; MainLoop
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
MainLoop:
|
||||
|
||||
;Output yellow led-status
|
||||
LEDy: SBRC pulseFlag,LEDyellowActive ; Check if LEDyellowActive is set
|
||||
RJMP LEDyON
|
||||
LEDyOFF: CBI PORTD,LEDyellow ; LEDyellow OFF (No Error)
|
||||
RJMP LEDr
|
||||
LEDyON: SBI PORTD,LEDyellow ; LEDyellow ON (Error detected)
|
||||
|
||||
;Output red led-status
|
||||
LEDr: SBRC pulseFlag,LEDredActive ; Check if LEDredActive is set
|
||||
RJMP LEDrON
|
||||
LEDrOFF: CBI PORTD,LEDred ; LEDred OFF (No Error)
|
||||
RJMP CheckButton
|
||||
LEDrON: SBI PORTD,LEDred ; LEDred ON (Error detected)
|
||||
RJMP MainLoop
|
||||
|
||||
;Save FailSafe-Value in EEPROM if button/jumper activated
|
||||
CheckButton:SBIC PIND,StoreButton ; Check if button pressed
|
||||
CLR debounceFilter ; Clear debounce register
|
||||
INC debounceFilter ; Incerment debounce register
|
||||
BRNE MainLoop
|
||||
|
||||
BPressed: CLI ; Disable GlobalInterrupt
|
||||
SBI PORTD,LEDyellow ; Led ON (Work in progress)
|
||||
CLR temp
|
||||
OUT PORTB,temp ; PORTB = 0x00
|
||||
CLR chAddressEE ; Clear chAddressEE register
|
||||
SwitchBuffert ; Switch Buffert in SRAM
|
||||
|
||||
CopyPulseSE:Read16SRAM chAddressEE,tempH,tempL ; Copy SRAM to temp
|
||||
Write16EEPROM chAddressEE,tempH,tempL ; Copy temp to EEPROM
|
||||
INC chAddressEE ; Increment chAddressEE twice
|
||||
INC chAddressEE
|
||||
CPI chAddressEE,((NrOfChannels*2)+2) ; Check if chAddressFE ==
|
||||
BRNE CopyPulseSE ; ((NrOfChannels*2)+2)
|
||||
CBI PORTD,LEDyellow ; Led OFF (Work complete)
|
||||
SwitchBuffert ; Switch Buffert in SRAM
|
||||
|
||||
ButtonLoop: SBIS PIND,StoreButton ; Check if button pressed
|
||||
RJMP ButtonLoop
|
||||
SEI ; Enable GlobalInterrupt
|
||||
RJMP MainLoop
|
||||
|
||||
;==========================================================================================================
|
||||
; END
|
||||
;==========================================================================================================
|
||||
658
PPMDecoder/ASM/RCRXDecoderV2.asm
Executable file
658
PPMDecoder/ASM/RCRXDecoderV2.asm
Executable file
@ -0,0 +1,658 @@
|
||||
;==========================================================================================================
|
||||
;
|
||||
; CMtec RCRXDecoder copyright 2005 v1.0 (2005-01-23)
|
||||
;
|
||||
; Name: Christoffer Martinsson
|
||||
; E-mail: cm@wsm.se
|
||||
;
|
||||
; 7ch PPM decoder for RC-Receivers.
|
||||
; Based on Atmel AT90S2313 or ATTiny2313 with 10 or 20Mhz crystal.
|
||||
;
|
||||
; PORTB,PB0-PB7 assign to output ch 1 to ch 7 (ch 8 reserved)
|
||||
; PORTD,PD2 assign to input PPM-signal from RX
|
||||
; PORTD,PD3 assign to StoreButton
|
||||
; PORTD,PD4 assign to LED
|
||||
;
|
||||
; The inputsignal is decoded into two separate buffert locations in the SRAM. The output-routine work
|
||||
; with the buffert that the input-routine NOT work with. After a "good" frame is decoded the buffertPointer
|
||||
; is switch. This to ensure that a "good" pulseframe allways is available if a error should occur.
|
||||
;
|
||||
; Flowchart: RCRXDecoder.vsd
|
||||
;
|
||||
; * Up to 8 channels
|
||||
; * 100step/ms resolution at 10Mhz, 200step/ms resolution at 20Mhz
|
||||
; * Allways a "good" output-signal
|
||||
; * Output is "Freezed" if error occurs
|
||||
; * Failsafe sets predefined values if error not recovered in (recomended) 2sec (max 8sec/10Mhz, 4sec/20Mhz)
|
||||
; * Failsafe-value easily changed by pressing a button
|
||||
; * PulseValue filtered to a smooth average-value
|
||||
; * Error/Glitch indicator
|
||||
;
|
||||
;==========================================================================================================
|
||||
; Processor-type
|
||||
.EQU AT90S2313 = 1
|
||||
;EQU ATTiny2313 = 1
|
||||
|
||||
.NOLIST ; Disable listfile generation
|
||||
.ifdef AT90S2313
|
||||
.INCLUDE "2313def.inc"
|
||||
.else
|
||||
.INCLUDE "tn2313def.inc"
|
||||
.endif
|
||||
.LIST ; Reenable listfile generation
|
||||
|
||||
; General definitions
|
||||
; Adjust this numbers to make it work propely with your application
|
||||
|
||||
.EQU XTAL =10 ; Used crystal (Mhz) (min 10Mhz)
|
||||
.EQU RecoveryNr =1 ; Number of "good" pulseFrames to recover from error-state
|
||||
.EQU NrOfChannels =7 ; Numbers of channels (max 8)
|
||||
.EQU FailSafeTime =2 ; Time before enter failsafe (sec) (max 8sec/10Mhz, 4sec/20Mhz)
|
||||
|
||||
; 8bit register
|
||||
.DEF temp =r16 ; Temporary register
|
||||
.DEF nextSRAMAddress =r12 ; Register for storing secondary SRAMAddress (buffert2)
|
||||
.DEF debounceFilter =r15 ; Button-debounce register
|
||||
.DEF timeout =r17 ; Timeout counter
|
||||
.DEF chAddressEE =r18 ; EEPROM channelAddress
|
||||
.DEF chAddressIn =r19 ; Input channelAddress
|
||||
.DEF chAddressOut =r20 ; Output channelAddress
|
||||
.DEF chAddressFS =r21 ; Failsafe channelAddress
|
||||
.DEF pulseError =r22 ; PulseErrorCounter
|
||||
.DEF pulseFlag =r23 ; Flag register
|
||||
|
||||
; "16bit" register
|
||||
.DEF frameCalcL =r13 ; Register for calculate FrameTime
|
||||
.DEF frameCalcH =r14
|
||||
.DEF tempL =r24 ; Temporary register
|
||||
.DEF tempH =r25
|
||||
.DEF pulseInL =r26 ; InputPulseCounter
|
||||
.DEF pulseInH =r27
|
||||
.DEF pulseOutL =r28 ; OutputPulseCounter
|
||||
.DEF pulseOutH =r29
|
||||
|
||||
; pulseFlag bit-definitions
|
||||
.EQU SYNC =0 ; Sync found-Flag
|
||||
.EQU LEDredActive =1 ; LEDred Active-Flag
|
||||
.EQU LEDyellowActive =2 ; LEDyellow Active-Flag
|
||||
.EQU BuffertToUse =3 ; Buffert-Flag (0=buffert1, 1=buffert2)
|
||||
|
||||
; Output bit-definitions
|
||||
.EQU PPMSignal =2 ; PD2 Input for PPM-signal
|
||||
.EQU StoreButton =3 ; PD3 Input for StoreButton
|
||||
.EQU LEDred =4 ; PD4 Output for LEDred
|
||||
.EQU LEDyellow =5 ; PD4 Output for LEDyellow
|
||||
|
||||
; Memory definitions
|
||||
.EQU SRAMaddress1 =0x0060 ; Startlocation for buffert1 in SRAM
|
||||
.EQU SRAMAddress2 =0x0074 ; Startlocation for buffert2 in SRAM
|
||||
.EQU EEPROMaddress =0x0000 ; Startlocation for failsafe-storage in EEPROM
|
||||
|
||||
; Time definitions (timer0)
|
||||
.EQU FSTimeoutTime =(2*XTAL*FailSafeTime) ; 1sec*FailSafeTime
|
||||
|
||||
; Time definitions (timer1)
|
||||
.EQU MinPulseTime =(95*(XTAL/10)) ; ~0,95ms
|
||||
.EQU MaxPulseTime =(220*(XTAL/10)) ; ~2,2ms
|
||||
.EQU MinSyncTime =(400*(XTAL/10)) ; ~4ms
|
||||
.EQU MaxSyncTime =(1400*(XTAL/10)) ; ~14ms
|
||||
.EQU FrameTime =(1950*(XTAL/10)) ; ~20ms
|
||||
|
||||
.CSEG ; CODE segment
|
||||
.ORG 0
|
||||
;==========================================================================================================
|
||||
; Reset- and Interrupt-vectors
|
||||
;==========================================================================================================
|
||||
RJMP Main ; Reset Handler
|
||||
RJMP Ex_Int0 ; External Interrupt0 Handler
|
||||
RETI ; External Interrupt1 Handler
|
||||
RETI ; Timer1 Capture Handler
|
||||
RJMP Timer_Int1 ; Timer1 CompareA Handler
|
||||
RETI ; Timer1 Overflow Handler
|
||||
RJMP Timer_Int0 ; Timer0 Overflow Handler
|
||||
RETI ; USART0 RX Complete Handler
|
||||
RETI ; USART0,UDR Empty Handler
|
||||
RETI ; USART0 TX Complete Handler
|
||||
RETI ; Analog Comparator Handler
|
||||
|
||||
.ifdef ATTiny2313
|
||||
|
||||
RETI ; Pin Change Interrupt
|
||||
RETI ; Timer1 Compare B Handler
|
||||
RETI ; Timer0 Compare A Handler
|
||||
RETI ; Timer0 Compare B Handler
|
||||
RETI ; USI Start Handler
|
||||
RETI ; USI Overflow Handler
|
||||
RETI ; EEPROM Ready Handler
|
||||
RETI ; Watchdog Overflow Handler
|
||||
.endif
|
||||
;==========================================================================================================
|
||||
; Macro
|
||||
;==========================================================================================================
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Load16Temp
|
||||
;
|
||||
; Description: Load 16bit tempReg with 16bit @0-value
|
||||
;
|
||||
; Input: @0,@1
|
||||
; ChangedReg: tempH,tempL
|
||||
; UsedReg: tempH,tempL
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO Load16Temp
|
||||
LDI tempH,HIGH(@0)
|
||||
LDI tempL,LOW(@0)
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Compare16Temp
|
||||
;
|
||||
; Description: Compare 16bit tempReg with 16bit @0,@1-reg
|
||||
;
|
||||
; Input: @0,@1
|
||||
; ChangedReg: Carry
|
||||
; UsedReg: tempH,tempL
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO Compare16Temp
|
||||
CP tempL,@1
|
||||
CPC tempH,@0
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Clear16Reg
|
||||
;
|
||||
; Description: Clear 16bit @0,@1-register
|
||||
;
|
||||
; Input: @0,@1
|
||||
; ChangedReg: @0,@1
|
||||
; UsedReg: -
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO Clear16Reg
|
||||
CLR @0
|
||||
CLR @1
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Add16Reg
|
||||
;
|
||||
; Description: Add 16bit @2,@3 to 16bit @0,@1
|
||||
;
|
||||
; Input: @0,@1
|
||||
; ChangedReg: @0,@1,Carry
|
||||
; UsedReg: -
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO Add16Reg
|
||||
ADD @1,@3
|
||||
ADC @0,@2
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Sub16Reg
|
||||
;
|
||||
; Description: Subtract 16bit @2,@3 from 16bit @0,@1
|
||||
;
|
||||
; Input: @0,@1
|
||||
; ChangedReg: @0,@1,Carry
|
||||
; UsedReg: -
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO Sub16Reg
|
||||
SUB @1,@3
|
||||
SBC @0,@2
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; DivByTwo16Reg
|
||||
;
|
||||
; Description: Divide 16bit @0,@1 by two
|
||||
;
|
||||
; Input: @0,@1
|
||||
; ChangedReg: @0,@1
|
||||
; UsedReg: -
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO DivByTwo16Reg
|
||||
CLC
|
||||
ROR @0
|
||||
ROR @1
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Write16SRAM
|
||||
;
|
||||
; Description: Write data in 16bit @1,@2-reg to SRAM at position @0
|
||||
;
|
||||
; (BuffertToUse-Flag: 0=buffert1, 1=buffert2)
|
||||
;
|
||||
; Input: @0,@1,@2
|
||||
; ChangedReg: -
|
||||
; UsedReg: ZL,pulseFlag
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO Write16SRAM
|
||||
LDI ZL,LOW(SRAMaddress1)
|
||||
SBRC pulseFlag,BuffertToUse
|
||||
ADD ZL,nextSRAMAddress
|
||||
ADD ZL,@0
|
||||
ST Z+,@1
|
||||
ST Z,@2
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Read16SRAM
|
||||
;
|
||||
; Description: Read data in SRAM at position @0 to 16bir @1,@2-reg
|
||||
;
|
||||
; (BuffertToUse-Flag: 0=buffert1, 1=buffert2)
|
||||
;
|
||||
; Input: @0,@1,@2
|
||||
; ChangedReg: @1,@2
|
||||
; UsedReg: ZL,pulseFlag
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO Read16SRAM
|
||||
LDI ZL,LOW(SRAMaddress1)
|
||||
SBRC pulseFlag,BuffertToUse
|
||||
ADD ZL,nextSRAMAddress
|
||||
ADD ZL,@0
|
||||
LD @1,Z+
|
||||
LD @2,Z
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Write16EEPROM
|
||||
;
|
||||
; Description: Write data in 16bit @1,@2-reg to EEPROM at position @0
|
||||
;
|
||||
; Input: @0,@1,@2
|
||||
; ChangedReg: -
|
||||
; UsedReg: temp,EECR,EEARL,EEDR
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO Write16EEPROM
|
||||
MWEEWait1: SBIC EECR,1
|
||||
RJMP MWEEWait1
|
||||
LDI temp,LOW(EEPROMaddress)
|
||||
ADD temp,@0
|
||||
OUT EEARL,temp
|
||||
OUT EEDR,@1
|
||||
SBI EECR,EEMWE
|
||||
SBI EECR,EEWE
|
||||
|
||||
MWEEWait2: SBIC EECR,1
|
||||
RJMP MWEEWait2
|
||||
LDI temp,LOW(EEPROMaddress)
|
||||
ADD temp,@0
|
||||
INC temp
|
||||
OUT EEARL,temp
|
||||
OUT EEDR,@2
|
||||
SBI EECR,EEMWE
|
||||
SBI EECR,EEWE
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Read16EEPROM
|
||||
;
|
||||
; Description: Read data in EEPROM at position @0 to 16bir @1,@2-reg
|
||||
;
|
||||
; Input: @0,@1,@2
|
||||
; ChangedReg: @1,@2
|
||||
; UsedReg: temp,EECR,EEARL,EEDR
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO Read16EEPROM
|
||||
MREEWait1: SBIC EECR,1
|
||||
RJMP MREEWait1
|
||||
LDI temp,LOW(EEPROMaddress)
|
||||
ADD temp,@0
|
||||
OUT EEARL,temp
|
||||
SBI EECR,EERE
|
||||
IN @1,EEDR
|
||||
|
||||
MREEWait2: SBIC EECR,1
|
||||
RJMP MREEWait2
|
||||
LDI temp,LOW(EEPROMaddress)
|
||||
ADD temp,@0
|
||||
INC temp
|
||||
OUT EEARL,temp
|
||||
SBI EECR,EERE
|
||||
IN @2,EEDR
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; StartTimer0
|
||||
;
|
||||
; Description: Start timer0. Prescale set to CK/1024
|
||||
;
|
||||
; Input: -
|
||||
; ChangedReg: -
|
||||
; UsedReg: temp,TCCR0
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO StartTimer0
|
||||
LDI temp,0x05
|
||||
OUT TCCR0,temp ; Prescale set to CK/1024
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; StopTimer0
|
||||
;
|
||||
; Description: Stop timer0
|
||||
;
|
||||
; Input: -
|
||||
; ChangedReg: -
|
||||
; UsedReg: temp,TCCR0
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO StopTimer0
|
||||
CLR temp
|
||||
OUT TCCR0,temp
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; StartTimer1
|
||||
;
|
||||
; Description: Star timer1. Prescale set to CK
|
||||
;
|
||||
; Input: -
|
||||
; ChangedReg: -
|
||||
; UsedReg: temp,OCR1AH,OCR1AL,TCCR1B
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO StartTimer1
|
||||
LDI temp,HIGH(100)
|
||||
OUT OCR1AH,temp
|
||||
LDI temp,LOW(100)
|
||||
OUT OCR1AL,temp
|
||||
LDI temp,0x09
|
||||
OUT TCCR1B,temp ; Prescale set to CK
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; StopTimer1
|
||||
;
|
||||
; Description: Stop timer1
|
||||
;
|
||||
; Input: -
|
||||
; ChangedReg: -
|
||||
; UsedReg: temp,TCCR1B
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO StopTimer1
|
||||
CLR temp
|
||||
OUT TCCR1B,temp
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; StoreTempOnStack
|
||||
;
|
||||
; Description: Store Status and temp-register on Stack
|
||||
;
|
||||
; Input: -
|
||||
; ChangedReg: -
|
||||
; UsedReg: temp,tempH,tempL,SREG
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO StoreTempOnStack
|
||||
PUSH tempH
|
||||
PUSH tempL
|
||||
PUSH temp
|
||||
IN temp,SREG
|
||||
PUSH temp
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; RestoreTempFromStack
|
||||
;
|
||||
; Description: Restore Status and temp-register from Stack
|
||||
;
|
||||
; Input: -
|
||||
; ChangedReg: temp,tempH,tempL,SREG
|
||||
; UsedReg: temp,tempH,tempL,SREG
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO RestoreTempFromStack
|
||||
POP temp
|
||||
OUT SREG,temp
|
||||
POP temp
|
||||
POP tempL
|
||||
POP tempH
|
||||
.ENDMACRO
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; SwitchBuffert
|
||||
;
|
||||
; Description: Switches buffertPointer in SRAM (BuffertToUse-Flag: 0=buffert1, 1=buffert2)
|
||||
;
|
||||
; Input: -
|
||||
; ChangedReg: pulseFlag
|
||||
; UsedReg: temp,pulseFlag
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
.MACRO SwitchBuffert
|
||||
LDI temp,(1<<BuffertToUse)
|
||||
EOR pulseFlag,temp ; Switch Buffert in SRAM
|
||||
.ENDMACRO
|
||||
;==========================================================================================================
|
||||
; Interrupt routines
|
||||
;==========================================================================================================
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Ex_Int0
|
||||
;
|
||||
; Description: Measure incoming pulse-value, filter it and then store it in SRAM.
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
Ex_Int0: StoreTempOnStack
|
||||
|
||||
ChkSync: SBRC pulseFlag,SYNC ; Check if sync found
|
||||
RJMP ChkError
|
||||
Load16Temp MinSyncTime
|
||||
Compare16Temp pulseInH,pulseInL ; Chrck if pulseIn > MinSyncTime
|
||||
BRCC Error;
|
||||
Load16Temp MaxSyncTime
|
||||
Compare16Temp pulseInH,pulseInL ; Check if pulseIn < MaxSyncTime
|
||||
BRCS Error
|
||||
SBR pulseFlag,(1<<SYNC) ; SYNC-Flag set
|
||||
CLR chAddressIn ; Clear chAddressIn
|
||||
|
||||
ChkSyncExit:Clear16Reg pulseInH,pulseInL ; Clear pulseIn register
|
||||
RestoreTempFromStack
|
||||
RETI
|
||||
|
||||
ChkError: Load16Temp MinPulseTime
|
||||
Compare16Temp pulseInH,pulseInL ; Check if pulseIn > MinPulseTime
|
||||
BRCC Error
|
||||
Load16Temp MaxPulseTime
|
||||
Compare16Temp pulseInH,pulseInL ; Check if pulseIn < MaxPulseTime
|
||||
BRCS Error
|
||||
|
||||
CPI pulseError,0 ; Check if pulseError == 0
|
||||
BREQ NoError
|
||||
DEC pulseError ; Decrement pulseError
|
||||
|
||||
INC chAddressIn ; Increment pulseOut-address twice
|
||||
INC chAddressIn
|
||||
CPI chAddressIn,(NrOfChannels*2) ; Check if chAddress == (NrOfChannels*2)
|
||||
BRNE ChkErrExit
|
||||
CBR pulseFlag,(1<<SYNC) ; Clear SYNC-Flag
|
||||
Clear16Reg frameCalcH,frameCalcL ; Clear FrameCalculation register
|
||||
|
||||
ChkErrExit: Clear16Reg pulseInH,pulseInL ; Clear pulseIn register
|
||||
RestoreTempFromStack
|
||||
RETI
|
||||
|
||||
Error: CBR pulseFlag,(1<<SYNC) ; SYNC-Flagg cleared
|
||||
SBR pulseFlag,(1<<LEDredActive) ; LEDActive-Flag set
|
||||
LDI pulseError,(RecoveryNr*NrOfChannels); pulseError = (RecoveryNr*NrOfChannels)
|
||||
|
||||
ErrorExit: Clear16Reg pulseInH,pulseInL ; Clear pulseIn register
|
||||
RestoreTempFromStack
|
||||
RETI
|
||||
|
||||
NoError: CLR timeout ; Clear timeout register
|
||||
CLR chAddressFS ; Clear chAddressEE
|
||||
StartTimer0 ; Start timer0
|
||||
|
||||
Read16SRAM chAddressIn,tempH,tempL ; Copy SRAM to temp
|
||||
Add16Reg pulseInH,pulseInL,tempH,tempL ; Add past value to current value
|
||||
DivByTwo16Reg pulseInH,pulseInL ; Divide value by two
|
||||
|
||||
Write16SRAM chAddressIn,pulseInH,pulseInL ; Copy temp to SRAM
|
||||
Add16Reg frameCalcH,frameCalcL,pulseInH,pulseInL; Add curren value to frameCalc register
|
||||
|
||||
INC chAddressIn ; Increment pulseOut-address twice
|
||||
INC chAddressIn
|
||||
CPI chAddressIn,(NrOfChannels*2) ; Check if chAddress == (NrOfChannels*2)
|
||||
BRNE NoErrorExit
|
||||
CBR pulseFlag,(1<<SYNC) ; Clear SYNC-Flag
|
||||
|
||||
Load16Temp FrameTime
|
||||
Sub16Reg tempH,tempL,frameCalcH,frameCalcL ; Calculate frame-time
|
||||
Write16SRAM chAddressIn,tempH,tempL ; Write frame-time to SRAM
|
||||
|
||||
SwitchBuffert ; Switch Buffert in SRAM
|
||||
CBR pulseFlag,(1<<LEDredActive) ; LEDredActive-Flag cleared
|
||||
CBR pulseFlag,(1<<LEDyellowActive) ; LEDywllowActive-Flag cleared
|
||||
|
||||
Clear16Reg frameCalcH,frameCalcL ; Clear frameCalc register
|
||||
|
||||
NoErrorExit:Clear16Reg pulseInH,pulseInL ; Clear pulseIn register
|
||||
RestoreTempFromStack
|
||||
RETI
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Timer_Int1
|
||||
;
|
||||
; Description: Increment pulseIn and pulseOut counter-registers
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
Timer_Int1: ADIW pulseInL,1 ; Increment pulseIn register
|
||||
ADIW pulseOutL,1 ; Increment pulseOut register
|
||||
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; Timer_Int0
|
||||
;
|
||||
; Description: Failsafe "watchdog". Restore pulse-value from EEPROM to SRAM if timeout occurs.
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
Timer_Int0: StoreTempOnStack
|
||||
CPI timeout,FStimeoutTime ; Check if timeout == FailsafeTime
|
||||
BREQ CopyPulseES
|
||||
INC timeout ; Increment timeout
|
||||
RestoreTempFromStack
|
||||
RETI
|
||||
|
||||
CopyPulseES:SBR pulseFlag,(1<<LEDyellowActive) ; LEDActive-Flgg set
|
||||
Read16EEPROM chAddressFS,tempH,tempL ; Copy EEPROM to temp
|
||||
Write16SRAM chAddressFS,tempH,tempL ; Copy temp to SRAM
|
||||
SwitchBuffert ; Switch Buffert in SRAM
|
||||
Write16SRAM chAddressFS,tempH,tempL ; Copy temp to SRAM
|
||||
SwitchBuffert ; Switch Buffert in SRAM
|
||||
INC chAddressFS ; Increment chAddressFS twice
|
||||
INC chAddressFS
|
||||
CPI chAddressFS,((NrOfChannels*2)+2) ; Check if chAddressFS ==
|
||||
BRNE NextPulseES ; ((NrOfChannels*2)+2)
|
||||
StopTimer0 ; Stop timer0
|
||||
|
||||
NextPulseES:RestoreTempFromStack
|
||||
RETI
|
||||
|
||||
;==========================================================================================================
|
||||
; Main
|
||||
;==========================================================================================================
|
||||
Main: LDI temp,LOW(RAMEND)
|
||||
OUT SPL,temp ; Set StackPointeradress
|
||||
|
||||
CLI ; Disable GlobalInterrupt
|
||||
|
||||
LDI temp,0xFF
|
||||
OUT DDRB,temp ; All output on PORTB
|
||||
SBI DDRD,LEDred ; All input except PIN"LEDred"
|
||||
SBI DDRD,LEDyellow ; and PIN"LEDyellow"
|
||||
SBI PORTD,PPMSignal ; Enable pullup on INT0 input
|
||||
SBI PORTD,StoreButton ; Enable pullup on StoreButton input
|
||||
|
||||
LDI temp,(1<<INT0)
|
||||
OUT GIMSK,temp ; Enable external interrupt 0
|
||||
LDI temp,(1<<ISC01)
|
||||
OUT MCUCR,temp ; Trigg on falling edge
|
||||
LDI temp,(1<<OCIE1A)|(1<<TOIE0)
|
||||
OUT TIMSK,temp ; Enable internal timer0
|
||||
; and timer1 interrupt
|
||||
CLR chAddressOut ; Clear register
|
||||
CLR chAddressIn
|
||||
CLR chAddressFS
|
||||
CLR timeout
|
||||
CLR pulseFlag
|
||||
|
||||
CLR ZH ; Clear Z-Pointer MSB
|
||||
|
||||
Clear16Reg pulseInH,pulseInL ; Clear pulseIn-Reg
|
||||
Clear16Reg pulseOutH,pulseOutL ; Clear pulseOut-Reg
|
||||
|
||||
LDI temp,(LOW(SRAMAddress2)-SRAMAddress1)
|
||||
MOV nextSRAMAddress,temp ; Set nextSRAMAddress
|
||||
|
||||
InitMemES: Read16EEPROM chAddressEE,tempH,tempL ; Copy pulse-value from EEPROM to SRAM
|
||||
Write16SRAM chAddressEE,tempH,tempL
|
||||
SwitchBuffert ; Switch Buffert in SRAM
|
||||
Write16SRAM chAddressEE,tempH,tempL
|
||||
SwitchBuffert ; Switch Buffert in SRAM
|
||||
INC chAddressEE
|
||||
INC chAddressEE
|
||||
CPI chAddressEE,((NrOfChannels*2)+2);
|
||||
BRNE InitMemES
|
||||
|
||||
CBR pulseFlag,(1<<SYNC) ; Generate error
|
||||
SBR pulseFlag,(1<<LEDredActive)
|
||||
LDI pulseError,(RecoveryNr*NrOfChannels)
|
||||
|
||||
SEI ; Enable GlobalInterrupt
|
||||
|
||||
StartTimer1 ; Start timer1
|
||||
StartTimer0 ; Start timer0
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
; MainLoop
|
||||
;----------------------------------------------------------------------------------------------------------
|
||||
MainLoop:
|
||||
; Generate output-pulses from SRAM to PORTB.
|
||||
|
||||
CPI chAddressOut,0 ; Check if chAddressOut == 0
|
||||
BRNE ReadOPulse
|
||||
LDI temp,0x01
|
||||
OUT PORTB,temp ; PORTB = 0x01
|
||||
|
||||
|
||||
ReadOPulse: ;SwitchBuffert ; Switch Buffert in SRAM
|
||||
Read16SRAM chAddressOut,tempH,tempL ; Copy SRAM to temp
|
||||
;SwitchBuffert ; Switch Buffert in SRAM
|
||||
Compare16Temp pulseOutH,pulseOutL ; Check if pulseOut < temp
|
||||
BRCS NextOPulse
|
||||
|
||||
RJMP ExitOPulse
|
||||
|
||||
NextOPulse: CPI chAddressOut,(NrOfChannels*2) ; Check if chAddressOut ==
|
||||
BREQ ResetOPulse ; (NrOfChannels*2)
|
||||
IN temp,PORTB
|
||||
LSL temp
|
||||
OUT PORTB,temp ; Roll PORTB left
|
||||
INC chAddressOut ; Increment chAddressOut twice
|
||||
INC chAddressOut
|
||||
Clear16Reg pulseOutH,pulseOutL ; Clear pulseOut register
|
||||
|
||||
RJMP ExitOPulse
|
||||
|
||||
ResetOPulse:CLR chAddressOut ; Clear chAddressOut register
|
||||
Clear16Reg pulseOutH,pulseOutL ; Clear pulseOut register
|
||||
ExitOPulse: RJMP MainLoop
|
||||
|
||||
;output yellow led-status
|
||||
LEDy: SBRC pulseFlag,LEDyellowActive ; Check if LEDyellowActive is set
|
||||
RJMP LEDyON
|
||||
LEDyOFF: CBI PORTD,LEDyellow ; LEDyellow OFF (No Error)
|
||||
RJMP LEDr
|
||||
LEDyON: SBI PORTD,LEDyellow ; LEDyellow ON (Error detected)
|
||||
|
||||
;output red led-status
|
||||
LEDr: SBRC pulseFlag,LEDredActive ; Check if LEDredActive is set
|
||||
RJMP LEDrON
|
||||
LEDrOFF: CBI PORTD,LEDred ; LEDred OFF (No Error)
|
||||
RJMP CheckButton
|
||||
LEDrON: SBI PORTD,LEDred ; LEDred ON (Error detected)
|
||||
RJMP MainLoop
|
||||
|
||||
CheckButton:SBIC PIND,StoreButton ; Check if button pressed
|
||||
CLR debounceFilter ; Clear debounce register
|
||||
INC debounceFilter ; Incerment debounce register
|
||||
BRNE MainLoop
|
||||
|
||||
BPressed: CLI ; Disable GlobalInterrupt
|
||||
SBI PORTD,LEDyellow ; Led ON (Work in progress)
|
||||
CLR temp
|
||||
OUT PORTB,temp ; PORTB = 0x00
|
||||
CLR chAddressEE ; Clear chAddressEE register
|
||||
SwitchBuffert ; Switch Buffert in SRAM
|
||||
|
||||
CopyPulseSE:Read16SRAM chAddressEE,tempH,tempL ; Copy SRAM to temp
|
||||
Write16EEPROM chAddressEE,tempH,tempL ; Copy temp to EEPROM
|
||||
INC chAddressEE ; Increment chAddressEE twice
|
||||
INC chAddressEE
|
||||
CPI chAddressEE,((NrOfChannels*2)+2) ; Check if chAddressFE ==
|
||||
BRNE CopyPulseSE ; ((NrOfChannels*2)+2)
|
||||
CBI PORTD,LEDyellow ; Led OFF (Work complete)
|
||||
SwitchBuffert ; Switch Buffert in SRAM
|
||||
|
||||
ButtonLoop: SBIS PIND,StoreButton ; Check if button pressed
|
||||
RJMP ButtonLoop
|
||||
SEI ; Enable GlobalInterrupt
|
||||
RJMP MainLoop
|
||||
|
||||
;==========================================================================================================
|
||||
; END
|
||||
;==========================================================================================================
|
||||
4
PPMDecoder/ASM/avrBuild.bat
Executable file
4
PPMDecoder/ASM/avrBuild.bat
Executable file
@ -0,0 +1,4 @@
|
||||
@ECHO OFF
|
||||
del "d:\-project-\rcrxdecoder\asm\rcrxdecoder.map"
|
||||
del "d:\-project-\rcrxdecoder\asm\labels.tmp"
|
||||
"C:\Program Files\Atmel\AVR Tools\AvrAssembler2\avrasm2.exe" -S "d:\-project-\rcrxdecoder\asm\labels.tmp" -fI -o "d:\-project-\rcrxdecoder\asm\rcrxdecoder.hex" -d "d:\-project-\rcrxdecoder\asm\rcrxdecoder.obj" -e "d:\-project-\rcrxdecoder\asm\rcrxdecoder.eep" -m "d:\-project-\rcrxdecoder\asm\rcrxdecoder.map" -W+ie "D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm"
|
||||
40
PPMDecoder/ASM/labels.tmp
Executable file
40
PPMDecoder/ASM/labels.tmp
Executable file
@ -0,0 +1,40 @@
|
||||
<ASSEMBLER_INFO>
|
||||
<WORKING_DIR>c:\</WORKING_DIR>
|
||||
<INCLUDE_PATH>
|
||||
<DIR>C:\Program Files\Atmel\AVR Tools\AvrAssembler2\Appnotes</DIR>
|
||||
</INCLUDE_PATH>
|
||||
<INCLUDED_FILES>
|
||||
<FILE>D:\-Project-\RCRXDecoder\ASM\2313def.inc</FILE>
|
||||
</INCLUDED_FILES>
|
||||
<LABELS>
|
||||
<Main><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>564</LINE></Main>
|
||||
<Ex_Int0><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>420</LINE></Ex_Int0>
|
||||
<Timer_Int1><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>502</LINE></Timer_Int1>
|
||||
<Timer_Int0><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>539</LINE></Timer_Int0>
|
||||
<ChkSync><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>422</LINE></ChkSync>
|
||||
<ChkError><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>437</LINE></ChkError>
|
||||
<Error><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>459</LINE></Error>
|
||||
<ChkSyncExit><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>433</LINE></ChkSyncExit>
|
||||
<NoError><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>467</LINE></NoError>
|
||||
<ChkErrExit><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>455</LINE></ChkErrExit>
|
||||
<ErrorExit><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>463</LINE></ErrorExit>
|
||||
<NoErrorExit><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>494</LINE></NoErrorExit>
|
||||
<ReadOPulse><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>511</LINE></ReadOPulse>
|
||||
<NextOPulse><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>519</LINE></NextOPulse>
|
||||
<ResetOPulse><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>530</LINE></ResetOPulse>
|
||||
<CopyPulseES><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>546</LINE></CopyPulseES>
|
||||
<NextPulseES><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>558</LINE></NextPulseES>
|
||||
<InitMemES><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>598</LINE></InitMemES>
|
||||
<MainLoop><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>621</LINE></MainLoop>
|
||||
<LEDy><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>624</LINE></LEDy>
|
||||
<LEDyON><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>628</LINE></LEDyON>
|
||||
<LEDyOFF><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>626</LINE></LEDyOFF>
|
||||
<LEDr><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>631</LINE></LEDr>
|
||||
<LEDrON><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>635</LINE></LEDrON>
|
||||
<LEDrOFF><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>633</LINE></LEDrOFF>
|
||||
<CheckButton><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>639</LINE></CheckButton>
|
||||
<BPressed><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>644</LINE></BPressed>
|
||||
<CopyPulseSE><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>651</LINE></CopyPulseSE>
|
||||
<ButtonLoop><FILE>D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm</FILE><LINE>660</LINE></ButtonLoop>
|
||||
</LABELS>
|
||||
</ASSEMBLER_INFO>
|
||||
1
PPMDecoder/ASM/rcrxdecoder.eep
Executable file
1
PPMDecoder/ASM/rcrxdecoder.eep
Executable file
@ -0,0 +1 @@
|
||||
:00000001FF
|
||||
374
PPMDecoder/ASM/rcrxdecoder.gen
Executable file
374
PPMDecoder/ASM/rcrxdecoder.gen
Executable file
@ -0,0 +1,374 @@
|
||||
000000:c0f0
|
||||
000001:c009
|
||||
000002:9518
|
||||
000003:9518
|
||||
000004:c07c
|
||||
000005:9518
|
||||
000006:c0b0
|
||||
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|
||||
000008:9518
|
||||
000009:9518
|
||||
00000a:9518
|
||||
00000b:939f
|
||||
00000c:938f
|
||||
00000d:930f
|
||||
00000e:b70f
|
||||
00000f:930f
|
||||
000010:fd70
|
||||
000011:c014
|
||||
000012:e091
|
||||
000013:e980
|
||||
000014:178a
|
||||
000015:079b
|
||||
000016:f558
|
||||
000017:e095
|
||||
000018:e788
|
||||
000019:178a
|
||||
00001a:079b
|
||||
00001b:f130
|
||||
00001c:6071
|
||||
00001d:2733
|
||||
00001e:27bb
|
||||
00001f:27aa
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
00005c:e6e0
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
0000b1:910f
|
||||
0000b2:bf0f
|
||||
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|
||||
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|
||||
0000b5:919f
|
||||
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|
||||
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|
||||
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|
||||
0000b9:930f
|
||||
0000ba:b70f
|
||||
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|
||||
0000bc:3218
|
||||
0000bd:f039
|
||||
0000be:9513
|
||||
0000bf:910f
|
||||
0000c0:bf0f
|
||||
0000c1:910f
|
||||
0000c2:918f
|
||||
0000c3:919f
|
||||
0000c4:9518
|
||||
0000c5:6074
|
||||
0000c6:99e1
|
||||
0000c7:cffe
|
||||
0000c8:e000
|
||||
0000c9:0f05
|
||||
0000ca:bb0e
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
0000d4:b38d
|
||||
0000d5:e6e0
|
||||
0000d6:fd73
|
||||
0000d7:0dec
|
||||
0000d8:0fe5
|
||||
0000d9:9391
|
||||
0000da:8380
|
||||
0000db:e008
|
||||
0000dc:2770
|
||||
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|
||||
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|
||||
0000df:0dec
|
||||
0000e0:0fe5
|
||||
0000e1:9391
|
||||
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|
||||
0000e3:e008
|
||||
0000e4:2770
|
||||
0000e5:9553
|
||||
0000e6:9553
|
||||
0000e7:3150
|
||||
0000e8:f411
|
||||
0000e9:2700
|
||||
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|
||||
0000eb:910f
|
||||
0000ec:bf0f
|
||||
0000ed:910f
|
||||
0000ee:918f
|
||||
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|
||||
0000f0:9518
|
||||
0000f1:ed0f
|
||||
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|
||||
0000f3:94f8
|
||||
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|
||||
0000f5:bd01
|
||||
0000f6:b908
|
||||
0000f7:ef0f
|
||||
0000f8:bb07
|
||||
0000f9:9a8c
|
||||
0000fa:9a8d
|
||||
0000fb:9a92
|
||||
0000fc:9a93
|
||||
0000fd:e400
|
||||
0000fe:bf0b
|
||||
0000ff:e002
|
||||
000100:bf05
|
||||
000101:e402
|
||||
000102:bf09
|
||||
000103:2744
|
||||
000104:2733
|
||||
000105:2755
|
||||
000106:2711
|
||||
000107:2777
|
||||
000108:27ff
|
||||
000109:27bb
|
||||
00010a:27aa
|
||||
00010b:27dd
|
||||
00010c:27cc
|
||||
00010d:e104
|
||||
00010e:2ec0
|
||||
00010f:99e1
|
||||
000110:cffe
|
||||
000111:e000
|
||||
000112:0f02
|
||||
000113:bb0e
|
||||
000114:9ae0
|
||||
000115:b39d
|
||||
000116:99e1
|
||||
000117:cffe
|
||||
000118:e000
|
||||
000119:0f02
|
||||
00011a:9503
|
||||
00011b:bb0e
|
||||
00011c:9ae0
|
||||
00011d:b38d
|
||||
00011e:e6e0
|
||||
00011f:fd73
|
||||
000120:0dec
|
||||
000121:0fe2
|
||||
000122:9391
|
||||
000123:8380
|
||||
000124:e008
|
||||
000125:2770
|
||||
000126:e6e0
|
||||
000127:fd73
|
||||
000128:0dec
|
||||
000129:0fe2
|
||||
00012a:9391
|
||||
00012b:8380
|
||||
00012c:e008
|
||||
00012d:2770
|
||||
00012e:9523
|
||||
00012f:9523
|
||||
000130:3120
|
||||
000131:f6e9
|
||||
000132:7f7e
|
||||
000133:6072
|
||||
000134:e067
|
||||
000135:9478
|
||||
000136:e000
|
||||
000137:bd0b
|
||||
000138:e604
|
||||
000139:bd0a
|
||||
00013a:e009
|
||||
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|
||||
00013c:e005
|
||||
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|
||||
00013e:fd72
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
000145:9894
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
00014d:94f8
|
||||
00014e:9a95
|
||||
00014f:2700
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
000156:0dec
|
||||
000157:0fe2
|
||||
000158:9191
|
||||
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|
||||
00015a:99e1
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
00015f:bb9d
|
||||
000160:9ae2
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
000165:0f02
|
||||
000166:9503
|
||||
000167:bb0e
|
||||
000168:bb8d
|
||||
000169:9ae2
|
||||
00016a:9ae1
|
||||
00016b:9523
|
||||
00016c:9523
|
||||
00016d:3120
|
||||
00016e:f729
|
||||
00016f:9895
|
||||
000170:e008
|
||||
000171:2770
|
||||
000172:9b83
|
||||
000173:cffe
|
||||
000174:9478
|
||||
000175:cfc8
|
||||
49
PPMDecoder/ASM/rcrxdecoder.hex
Executable file
49
PPMDecoder/ASM/rcrxdecoder.hex
Executable file
@ -0,0 +1,49 @@
|
||||
:020000020000FC
|
||||
:10000000F0C009C0189518957CC01895B0C0189517
|
||||
:100010001895189518959F938F930F930FB70F937B
|
||||
:1000200070FD14C091E080E98A179B0758F595E0B0
|
||||
:1000300088E78A179B0730F171603327BB27AA270F
|
||||
:100040000F910FBF0F918F919F91189590E08FE5C1
|
||||
:100050008A179B07B8F490E08CED8A179B0790F005
|
||||
:100060006030D9F06A95339533953E3019F47E7F30
|
||||
:10007000EE24DD24BB27AA270F910FBF0F918F918C
|
||||
:100080009F9118957E7F726067E0BB27AA270F912A
|
||||
:100090000FBF0F918F919F9118951127552705E05C
|
||||
:1000A00003BFE0E673FDEC0DE30F91918081A80F93
|
||||
:1000B000B91F8894B795A795E0E673FDEC0DE30FA3
|
||||
:1000C000B193A083DA0EEB1E339533953E3089F45D
|
||||
:1000D0007E7F97E08EE98D199E09E0E673FDEC0DB9
|
||||
:1000E000E30F9193808308E070277D7F7B7FEE2470
|
||||
:1000F000DD24BB27AA270F910FBF0F918F919F91EE
|
||||
:1001000018959F938F930F930FB70F931196219686
|
||||
:10011000403011F401E008BB08E07027E0E673FD11
|
||||
:10012000EC0DE40F9191808108E070278C179D07FA
|
||||
:1001300030F00F910FBF0F918F919F9118954E3016
|
||||
:1001400069F008B3000F08BB43954395DD27CC2722
|
||||
:100150000F910FBF0F918F919F9118954427DD2725
|
||||
:10016000CC270F910FBF0F918F919F9118959F935F
|
||||
:100170008F930F930FB70F93183239F013950F9198
|
||||
:100180000FBF0F918F919F9118957460E199FECFE9
|
||||
:1001900000E0050F0EBBE09A9DB3E199FECF00E0B1
|
||||
:1001A000050F03950EBBE09A8DB3E0E673FDEC0DF1
|
||||
:1001B000E50F9193808308E07027E0E673FDEC0D76
|
||||
:1001C000E50F9193808308E0702753955395503144
|
||||
:1001D00011F4002703BF0F910FBF0F918F919F91D3
|
||||
:1001E00018950FED0DBFF8940FEF07BB8C9A8D9A01
|
||||
:1001F000929A939A00E40BBF02E005BF02E409BFA4
|
||||
:10020000442733275527222711277727FF27BB2786
|
||||
:10021000AA27DD27CC2704E1C02EE199FECF00E01C
|
||||
:10022000020F0EBBE09A9DB3E199FECF00E0020FF2
|
||||
:1002300003950EBBE09A8DB3E0E673FDEC0DE20F83
|
||||
:100240009193808308E07027E0E673FDEC0DE20FE8
|
||||
:100250009193808308E07027239523952031E9F658
|
||||
:100260007E7F726067E0789400E00BBD04E60ABD13
|
||||
:1002700009E00EBD05E003BF72FD02C0959801C004
|
||||
:10028000959A71FD02C0949802C0949AF5CF839913
|
||||
:10029000FF24F39489F7F894959A002708BB222746
|
||||
:1002A00008E07027E0E673FDEC0DE20F919180818C
|
||||
:1002B000E199FECF00E0020F0EBB9DBBE29AE19AEE
|
||||
:1002C000E199FECF00E0020F03950EBB8DBBE29AD1
|
||||
:1002D000E19A23952395203129F7959808E0702716
|
||||
:0802E000839BFECF7894C8CF88
|
||||
:00000001FF
|
||||
318
PPMDecoder/ASM/rcrxdecoder.map
Executable file
318
PPMDecoder/ASM/rcrxdecoder.map
Executable file
@ -0,0 +1,318 @@
|
||||
|
||||
AVRASM ver. 2.0.28 D:\-Project-\RCRXDecoder\ASM\RCRXDecoder.asm Thu Apr 21 19:17:36 2005
|
||||
|
||||
|
||||
EQU at90s2313 00000001
|
||||
EQU signature_000 0000001e
|
||||
EQU signature_001 00000091
|
||||
EQU signature_002 00000001
|
||||
EQU sreg 0000003f
|
||||
EQU spl 0000003d
|
||||
EQU gimsk 0000003b
|
||||
EQU gifr 0000003a
|
||||
EQU timsk 00000039
|
||||
EQU tifr 00000038
|
||||
EQU mcucr 00000035
|
||||
EQU tccr0 00000033
|
||||
EQU tcnt0 00000032
|
||||
EQU tccr1a 0000002f
|
||||
EQU tccr1b 0000002e
|
||||
EQU tcnt1h 0000002d
|
||||
EQU tcnt1l 0000002c
|
||||
EQU ocr1ah 0000002b
|
||||
EQU ocr1al 0000002a
|
||||
EQU icr1h 00000025
|
||||
EQU icr1l 00000024
|
||||
EQU wdtcr 00000021
|
||||
EQU eear 0000001e
|
||||
EQU eedr 0000001d
|
||||
EQU eecr 0000001c
|
||||
EQU portb 00000018
|
||||
EQU ddrb 00000017
|
||||
EQU pinb 00000016
|
||||
EQU portd 00000012
|
||||
EQU ddrd 00000011
|
||||
EQU pind 00000010
|
||||
EQU udr 0000000c
|
||||
EQU usr 0000000b
|
||||
EQU ucr 0000000a
|
||||
EQU ubrr 00000009
|
||||
EQU acsr 00000008
|
||||
EQU portb0 00000000
|
||||
EQU pb0 00000000
|
||||
EQU portb1 00000001
|
||||
EQU pb1 00000001
|
||||
EQU portb2 00000002
|
||||
EQU pb2 00000002
|
||||
EQU portb3 00000003
|
||||
EQU pb3 00000003
|
||||
EQU portb4 00000004
|
||||
EQU pb4 00000004
|
||||
EQU portb5 00000005
|
||||
EQU pb5 00000005
|
||||
EQU portb6 00000006
|
||||
EQU pb6 00000006
|
||||
EQU portb7 00000007
|
||||
EQU pb7 00000007
|
||||
EQU ddb0 00000000
|
||||
EQU ddb1 00000001
|
||||
EQU ddb2 00000002
|
||||
EQU ddb3 00000003
|
||||
EQU ddb4 00000004
|
||||
EQU ddb5 00000005
|
||||
EQU ddb6 00000006
|
||||
EQU ddb7 00000007
|
||||
EQU pinb0 00000000
|
||||
EQU pinb1 00000001
|
||||
EQU pinb2 00000002
|
||||
EQU pinb3 00000003
|
||||
EQU pinb4 00000004
|
||||
EQU pinb5 00000005
|
||||
EQU pinb6 00000006
|
||||
EQU pinb7 00000007
|
||||
EQU toie0 00000001
|
||||
EQU tov0 00000001
|
||||
EQU cs00 00000000
|
||||
EQU cs01 00000001
|
||||
EQU cs02 00000002
|
||||
EQU tcnt00 00000000
|
||||
EQU tcnt01 00000001
|
||||
EQU tcnt02 00000002
|
||||
EQU tcnt03 00000003
|
||||
EQU tcnt04 00000004
|
||||
EQU tcnt05 00000005
|
||||
EQU tcnt06 00000006
|
||||
EQU tcnt07 00000007
|
||||
EQU ticie1 00000003
|
||||
EQU ocie1a 00000006
|
||||
EQU toie1 00000007
|
||||
EQU icf1 00000003
|
||||
EQU ocf1a 00000006
|
||||
EQU tov1 00000007
|
||||
EQU pwm10 00000000
|
||||
EQU pwm11 00000001
|
||||
EQU com1a0 00000006
|
||||
EQU com1a1 00000007
|
||||
EQU cs10 00000000
|
||||
EQU cs11 00000001
|
||||
EQU cs12 00000002
|
||||
EQU ctc1 00000003
|
||||
EQU ices1 00000006
|
||||
EQU icnc1 00000007
|
||||
EQU wdp0 00000000
|
||||
EQU wdp1 00000001
|
||||
EQU wdp2 00000002
|
||||
EQU wde 00000003
|
||||
EQU wdtoe 00000004
|
||||
EQU wdde 00000004
|
||||
EQU int0 00000006
|
||||
EQU int1 00000007
|
||||
EQU intf0 00000006
|
||||
EQU intf1 00000007
|
||||
EQU udr0 00000000
|
||||
EQU udr1 00000001
|
||||
EQU udr2 00000002
|
||||
EQU udr3 00000003
|
||||
EQU udr4 00000004
|
||||
EQU udr5 00000005
|
||||
EQU udr6 00000006
|
||||
EQU udr7 00000007
|
||||
EQU dor 00000003
|
||||
EQU fe 00000004
|
||||
EQU udre 00000005
|
||||
EQU txc 00000006
|
||||
EQU rxc 00000007
|
||||
EQU txb8 00000000
|
||||
EQU rxb8 00000001
|
||||
EQU chr9 00000002
|
||||
EQU txen 00000003
|
||||
EQU rxen 00000004
|
||||
EQU udrie 00000005
|
||||
EQU txcie 00000006
|
||||
EQU rxcie 00000007
|
||||
EQU ubrr0 00000000
|
||||
EQU ubrr1 00000001
|
||||
EQU ubrr2 00000002
|
||||
EQU ubrr3 00000003
|
||||
EQU ubrr4 00000004
|
||||
EQU ubrr5 00000005
|
||||
EQU ubrr6 00000006
|
||||
EQU ubrr7 00000007
|
||||
EQU acis0 00000000
|
||||
EQU acis1 00000001
|
||||
EQU acic 00000002
|
||||
EQU acie 00000003
|
||||
EQU aci 00000004
|
||||
EQU aco 00000005
|
||||
EQU acd 00000007
|
||||
EQU sreg_c 00000000
|
||||
EQU sreg_z 00000001
|
||||
EQU sreg_n 00000002
|
||||
EQU sreg_v 00000003
|
||||
EQU sreg_s 00000004
|
||||
EQU sreg_h 00000005
|
||||
EQU sreg_t 00000006
|
||||
EQU sreg_i 00000007
|
||||
EQU sp0 00000000
|
||||
EQU sp1 00000001
|
||||
EQU sp2 00000002
|
||||
EQU sp3 00000003
|
||||
EQU sp4 00000004
|
||||
EQU sp5 00000005
|
||||
EQU sp6 00000006
|
||||
EQU sp7 00000007
|
||||
EQU isc00 00000000
|
||||
EQU isc01 00000001
|
||||
EQU isc10 00000002
|
||||
EQU isc11 00000003
|
||||
EQU sm 00000004
|
||||
EQU se 00000005
|
||||
EQU portd0 00000000
|
||||
EQU pd0 00000000
|
||||
EQU portd1 00000001
|
||||
EQU pd1 00000001
|
||||
EQU portd2 00000002
|
||||
EQU pd2 00000002
|
||||
EQU portd3 00000003
|
||||
EQU pd3 00000003
|
||||
EQU portd4 00000004
|
||||
EQU pd4 00000004
|
||||
EQU portd5 00000005
|
||||
EQU pd5 00000005
|
||||
EQU portd6 00000006
|
||||
EQU pd6 00000006
|
||||
EQU ddd0 00000000
|
||||
EQU ddd1 00000001
|
||||
EQU ddd2 00000002
|
||||
EQU ddd3 00000003
|
||||
EQU ddd4 00000004
|
||||
EQU ddd5 00000005
|
||||
EQU ddd6 00000006
|
||||
EQU pind0 00000000
|
||||
EQU pind1 00000001
|
||||
EQU pind2 00000002
|
||||
EQU pind3 00000003
|
||||
EQU pind4 00000004
|
||||
EQU pind5 00000005
|
||||
EQU pind6 00000006
|
||||
EQU eearl 0000001e
|
||||
EQU eear0 00000000
|
||||
EQU eear1 00000001
|
||||
EQU eear2 00000002
|
||||
EQU eear3 00000003
|
||||
EQU eear4 00000004
|
||||
EQU eear5 00000005
|
||||
EQU eear6 00000006
|
||||
EQU eedr0 00000000
|
||||
EQU eedr1 00000001
|
||||
EQU eedr2 00000002
|
||||
EQU eedr3 00000003
|
||||
EQU eedr4 00000004
|
||||
EQU eedr5 00000005
|
||||
EQU eedr6 00000006
|
||||
EQU eedr7 00000007
|
||||
EQU eere 00000000
|
||||
EQU eewe 00000001
|
||||
EQU eemwe 00000002
|
||||
EQU lb1 00000000
|
||||
EQU lb2 00000001
|
||||
DEF xh r27
|
||||
DEF xl r26
|
||||
DEF yh r29
|
||||
DEF yl r28
|
||||
DEF zh r31
|
||||
DEF zl r30
|
||||
EQU flashend 000003ff
|
||||
EQU ioend 0000003f
|
||||
EQU sram_start 00000060
|
||||
EQU sram_size 00000080
|
||||
EQU ramend 000000df
|
||||
EQU xramend 00000000
|
||||
EQU e2end 0000007f
|
||||
EQU eepromend 0000007f
|
||||
EQU eeadrbits 00000007
|
||||
EQU int0addr 00000001
|
||||
EQU int1addr 00000002
|
||||
EQU icp1addr 00000003
|
||||
EQU oc1addr 00000004
|
||||
EQU ovf1addr 00000005
|
||||
EQU ovf0addr 00000006
|
||||
EQU urxcaddr 00000007
|
||||
EQU udreaddr 00000008
|
||||
EQU utxcaddr 00000009
|
||||
EQU aciaddr 0000000a
|
||||
EQU int_vectors_size 0000000b
|
||||
EQU xtal 0000000a
|
||||
EQU recoverynr 00000001
|
||||
EQU nrofchannels 00000007
|
||||
EQU failsafetime 00000002
|
||||
DEF temp r16
|
||||
DEF nextsramaddress r12
|
||||
DEF debouncefilter r15
|
||||
DEF timeout r17
|
||||
DEF chaddressee r18
|
||||
DEF chaddressin r19
|
||||
DEF chaddressout r20
|
||||
DEF chaddressfs r21
|
||||
DEF pulseerror r22
|
||||
DEF pulseflag r23
|
||||
DEF framecalcl r13
|
||||
DEF framecalch r14
|
||||
DEF templ r24
|
||||
DEF temph r25
|
||||
DEF pulseinl r26
|
||||
DEF pulseinh r27
|
||||
DEF pulseoutl r28
|
||||
DEF pulseouth r29
|
||||
EQU sync 00000000
|
||||
EQU ledredactive 00000001
|
||||
EQU ledyellowactive 00000002
|
||||
EQU bufferttouse 00000003
|
||||
EQU ppmsignal 00000002
|
||||
EQU storebutton 00000003
|
||||
EQU ledred 00000004
|
||||
EQU ledyellow 00000005
|
||||
EQU sramaddress1 00000060
|
||||
EQU sramaddress2 00000074
|
||||
EQU eepromaddress 00000000
|
||||
EQU fstimeouttime 00000028
|
||||
EQU minpulsetime 0000005f
|
||||
EQU maxpulsetime 000000dc
|
||||
EQU minsynctime 00000190
|
||||
EQU maxsynctime 00000578
|
||||
EQU frametime 0000079e
|
||||
CSEG main 000000f1
|
||||
CSEG ex_int0 0000000b
|
||||
CSEG timer_int1 00000081
|
||||
CSEG timer_int0 000000b7
|
||||
CSEG chksync 00000010
|
||||
CSEG chkerror 00000026
|
||||
CSEG error 00000042
|
||||
CSEG chksyncexit 0000001e
|
||||
CSEG noerror 0000004d
|
||||
CSEG chkerrexit 0000003a
|
||||
CSEG errorexit 00000045
|
||||
CSEG noerrorexit 00000079
|
||||
CSEG readopulse 0000008c
|
||||
CSEG nextopulse 0000009f
|
||||
CSEG resetopulse 000000ae
|
||||
CSEG copypulsees 000000c5
|
||||
CSEG mreewait1@read16eeprom@1126 000000c6
|
||||
CSEG mreewait2@read16eeprom@1126 000000cd
|
||||
CSEG nextpulsees 000000eb
|
||||
CSEG initmemes 0000010d
|
||||
CSEG mreewait1@read16eeprom@1229 0000010d
|
||||
CSEG mreewait2@read16eeprom@1229 00000114
|
||||
CSEG mainloop 0000013c
|
||||
CSEG ledy 0000013c
|
||||
CSEG ledyon 00000140
|
||||
CSEG ledyoff 0000013e
|
||||
CSEG ledr 00000141
|
||||
CSEG ledron 00000145
|
||||
CSEG ledroff 00000143
|
||||
CSEG checkbutton 00000147
|
||||
CSEG bpressed 0000014b
|
||||
CSEG copypulsese 00000152
|
||||
CSEG mweewait1@write16eeprom@1340 00000158
|
||||
CSEG mweewait2@write16eeprom@1340 00000160
|
||||
CSEG buttonloop 00000170
|
||||
51
PPMDecoder/ASM/rcrxdecoder.mot
Executable file
51
PPMDecoder/ASM/rcrxdecoder.mot
Executable file
@ -0,0 +1,51 @@
|
||||
S02F0000643A5C2D70726F6A6563742D5C726372786465636F6465725C61736D5C726372786465636F6465722E6D6F7488
|
||||
S1130000F8C011C01895189584C01895B8C01895F3
|
||||
S11300101895189518951895189518951895189574
|
||||
S11300201895189518959F938F930F930FB70F9367
|
||||
S113003070FD14C093E080E28A179B0758F59AE09C
|
||||
S113004080EF8A179B0730F171603327BB27AA27FB
|
||||
S11300500F910FBF0F918F919F91189590E08EEBA8
|
||||
S11300608A179B07B8F491E088EB8A179B0790F0F6
|
||||
S11300706030D9F06A95339533953E3019F47E7F1C
|
||||
S1130080EE24DD24BB27AA270F910FBF0F918F9178
|
||||
S11300909F9118957E7F726067E0BB27AA270F9116
|
||||
S11300A00FBF0F918F919F9118951127552705E048
|
||||
S11300B003BFE0E673FDEC0DE30F91918081A80F7F
|
||||
S11300C0B91F8894B795A795E0E673FDEC0DE30F8F
|
||||
S11300D0B193A083DA0EEB1E339533953E3089F449
|
||||
S11300E07E7F9FE08CE38D199E09E0E673FDEC0DA5
|
||||
S11300F0E30F9193808308E070277D7F7B7FEE245C
|
||||
S1130100DD24BB27AA270F910FBF0F918F919F91D9
|
||||
S113011018959F938F930F930FB70F931196219672
|
||||
S1130120403011F401E008BB08E07027E0E673FDFD
|
||||
S1130130EC0DE40F9191808108E070278C179D07E6
|
||||
S113014030F00F910FBF0F918F919F9118954E3002
|
||||
S113015069F008B3000F08BB43954395DD27CC270E
|
||||
S11301600F910FBF0F918F919F9118954427DD2711
|
||||
S1130170CC270F910FBF0F918F919F9118959F934B
|
||||
S11301808F930F930FB70F93103539F013950F9189
|
||||
S11301900FBF0F918F919F9118957460E199FECFD5
|
||||
S11301A000E0050F0EBBE09A9DB3E199FECF00E09D
|
||||
S11301B0050F03950EBBE09A8DB3E0E673FDEC0DDD
|
||||
S11301C0E50F9193808308E07027E0E673FDEC0D62
|
||||
S11301D0E50F9193808308E0702753955395503130
|
||||
S11301E011F4002703BF0F910FBF0F918F919F91BF
|
||||
S11301F018950FED0DBFF8940FEF07BB8C9A8D9AED
|
||||
S1130200929A939A00E40BBF02E005BF02E409BF8F
|
||||
S113021044273327552711277727FF27BB27AA27EA
|
||||
S1130220DD27CC2704E1C02EE199FECF00E0020FC8
|
||||
S11302300EBBE09A9DB3E199FECF00E0020F039557
|
||||
S11302400EBBE09A8DB3E0E673FDEC0DE20F9193E3
|
||||
S1130250808308E07027E0E673FDEC0DE20F9193D4
|
||||
S1130260808308E07027239523952031E9F67E7F6B
|
||||
S1130270726067E0789400E00BBD04E60ABD09E013
|
||||
S11302800EBD05E003BF72FD02C0959801C0959AAA
|
||||
S113029071FD02C0949802C0949AF5CF8399FF240B
|
||||
S11302A0F39489F7F894959A002708BB222708E06D
|
||||
S11302B07027E0E673FDEC0DE20F91918081E199E6
|
||||
S11302C0FECF00E0020F0EBB9DBBE29AE19AE199DA
|
||||
S11302D0FECF00E0020F03950EBB8DBBE29AE19ABC
|
||||
S11302E023952395203129F7959808E07027839B5F
|
||||
S10902F0FECF7894C8CF94
|
||||
S5030030CC
|
||||
S9030000FC
|
||||
BIN
PPMDecoder/ASM/rcrxdecoder.obj
Executable file
BIN
PPMDecoder/ASM/rcrxdecoder.obj
Executable file
Binary file not shown.
660
PPMDecoder/ASM/tn2313def.inc
Executable file
660
PPMDecoder/ASM/tn2313def.inc
Executable file
@ -0,0 +1,660 @@
|
||||
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
|
||||
;***** Created: 2005-01-11 10:31 ******* Source: ATtiny2313.xml **********
|
||||
;*************************************************************************
|
||||
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
|
||||
;*
|
||||
;* Number : AVR000
|
||||
;* File Name : "tn2313def.inc"
|
||||
;* Title : Register/Bit Definitions for the ATtiny2313
|
||||
;* Date : 2005-01-11
|
||||
;* Version : 2.14
|
||||
;* Support E-mail : avr@atmel.com
|
||||
;* Target MCU : ATtiny2313
|
||||
;*
|
||||
;* DESCRIPTION
|
||||
;* When including this file in the assembly program file, all I/O register
|
||||
;* names and I/O register bit names appearing in the data book can be used.
|
||||
;* In addition, the six registers forming the three data pointers X, Y and
|
||||
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
|
||||
;* SRAM is also defined
|
||||
;*
|
||||
;* The Register names are represented by their hexadecimal address.
|
||||
;*
|
||||
;* The Register Bit names are represented by their bit number (0-7).
|
||||
;*
|
||||
;* Please observe the difference in using the bit names with instructions
|
||||
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
|
||||
;* (skip if bit in register set/cleared). The following example illustrates
|
||||
;* this:
|
||||
;*
|
||||
;* in r16,PORTB ;read PORTB latch
|
||||
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
|
||||
;* out PORTB,r16 ;output to PORTB
|
||||
;*
|
||||
;* in r16,TIFR ;read the Timer Interrupt Flag Register
|
||||
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
|
||||
;* rjmp TOV0_is_set ;jump if set
|
||||
;* ... ;otherwise do something else
|
||||
;*************************************************************************
|
||||
|
||||
#ifndef _TN2313DEF_INC_
|
||||
#define _TN2313DEF_INC_
|
||||
|
||||
|
||||
#pragma partinc 0
|
||||
|
||||
; ***** SPECIFY DEVICE ***************************************************
|
||||
.device ATtiny2313
|
||||
#pragma AVRPART ADMIN PART_NAME ATtiny2313
|
||||
.equ SIGNATURE_000 = 0x1e
|
||||
.equ SIGNATURE_001 = 0x91
|
||||
.equ SIGNATURE_002 = 0x0a
|
||||
|
||||
#pragma AVRPART CORE CORE_VERSION V2
|
||||
#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+
|
||||
|
||||
|
||||
; ***** I/O REGISTER DEFINITIONS *****************************************
|
||||
; NOTE:
|
||||
; Definitions marked "MEMORY MAPPED"are extended I/O ports
|
||||
; and cannot be used with IN/OUT instructions
|
||||
.equ SREG = 0x3f
|
||||
.equ SPL = 0x3d
|
||||
.equ OCR0B = 0x3c
|
||||
.equ GIMSK = 0x3b
|
||||
.equ EIFR = 0x3a
|
||||
.equ TIMSK = 0x39
|
||||
.equ TIFR = 0x38
|
||||
.equ SPMCSR = 0x37
|
||||
.equ OCR0A = 0x36
|
||||
.equ MCUCR = 0x35
|
||||
.equ MCUSR = 0x34
|
||||
.equ TCCR0B = 0x33
|
||||
.equ TCNT0 = 0x32
|
||||
.equ OSCCAL = 0x31
|
||||
.equ TCCR0A = 0x30
|
||||
.equ TCCR1A = 0x2f
|
||||
.equ TCCR1B = 0x2e
|
||||
.equ TCNT1H = 0x2d
|
||||
.equ TCNT1L = 0x2c
|
||||
.equ OCR1AH = 0x2b
|
||||
.equ OCR1AL = 0x2a
|
||||
.equ OCR1BH = 0x29
|
||||
.equ OCR1BL = 0x28
|
||||
.equ CLKPR = 0x26
|
||||
.equ ICR1H = 0x25
|
||||
.equ ICR1L = 0x24
|
||||
.equ GTCCR = 0x23
|
||||
.equ TCCR1C = 0x22
|
||||
.equ WDTCR = 0x21
|
||||
.equ PCMSK = 0x20
|
||||
.equ EEAR = 0x1e
|
||||
.equ EEDR = 0x1d
|
||||
.equ EECR = 0x1c
|
||||
.equ PORTA = 0x1b
|
||||
.equ DDRA = 0x1a
|
||||
.equ PINA = 0x19
|
||||
.equ PORTB = 0x18
|
||||
.equ DDRB = 0x17
|
||||
.equ PINB = 0x16
|
||||
.equ GPIOR2 = 0x15
|
||||
.equ GPIOR1 = 0x14
|
||||
.equ GPIOR0 = 0x13
|
||||
.equ PORTD = 0x12
|
||||
.equ DDRD = 0x11
|
||||
.equ PIND = 0x10
|
||||
.equ USIDR = 0x0f
|
||||
.equ USISR = 0x0e
|
||||
.equ USICR = 0x0d
|
||||
.equ UDR = 0x0c
|
||||
.equ UCSRA = 0x0b
|
||||
.equ UCSRB = 0x0a
|
||||
.equ UBRRL = 0x09
|
||||
.equ ACSR = 0x08
|
||||
.equ UCSRC = 0x03
|
||||
.equ UBRRH = 0x02
|
||||
.equ DIDR = 0x01
|
||||
|
||||
|
||||
; ***** BIT DEFINITIONS **************************************************
|
||||
|
||||
; ***** PORTB ************************
|
||||
; PORTB - Port B Data Register
|
||||
.equ PORTB0 = 0 ; Port B Data Register bit 0
|
||||
.equ PB0 = 0 ; For compatibility
|
||||
.equ PORTB1 = 1 ; Port B Data Register bit 1
|
||||
.equ PB1 = 1 ; For compatibility
|
||||
.equ PORTB2 = 2 ; Port B Data Register bit 2
|
||||
.equ PB2 = 2 ; For compatibility
|
||||
.equ PORTB3 = 3 ; Port B Data Register bit 3
|
||||
.equ PB3 = 3 ; For compatibility
|
||||
.equ PORTB4 = 4 ; Port B Data Register bit 4
|
||||
.equ PB4 = 4 ; For compatibility
|
||||
.equ PORTB5 = 5 ; Port B Data Register bit 5
|
||||
.equ PB5 = 5 ; For compatibility
|
||||
.equ PORTB6 = 6 ; Port B Data Register bit 6
|
||||
.equ PB6 = 6 ; For compatibility
|
||||
.equ PORTB7 = 7 ; Port B Data Register bit 7
|
||||
.equ PB7 = 7 ; For compatibility
|
||||
|
||||
; DDRB - Port B Data Direction Register
|
||||
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
|
||||
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
|
||||
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
|
||||
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
|
||||
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
|
||||
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
|
||||
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
|
||||
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
|
||||
|
||||
; PINB - Port B Input Pins
|
||||
.equ PINB0 = 0 ; Port B Input Pins bit 0
|
||||
.equ PINB1 = 1 ; Port B Input Pins bit 1
|
||||
.equ PINB2 = 2 ; Port B Input Pins bit 2
|
||||
.equ PINB3 = 3 ; Port B Input Pins bit 3
|
||||
.equ PINB4 = 4 ; Port B Input Pins bit 4
|
||||
.equ PINB5 = 5 ; Port B Input Pins bit 5
|
||||
.equ PINB6 = 6 ; Port B Input Pins bit 6
|
||||
.equ PINB7 = 7 ; Port B Input Pins bit 7
|
||||
|
||||
|
||||
; ***** TIMER_COUNTER_0 **************
|
||||
; TIMSK - Timer/Counter Interrupt Mask Register
|
||||
.equ OCIE0A = 0 ; Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
|
||||
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
|
||||
; TIFR - Timer/Counter Interrupt Flag register
|
||||
.equ OCF0A = 0 ; Timer/Counter0 Output Compare Flag 0A
|
||||
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
|
||||
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B
|
||||
|
||||
; OCR0B - Timer/Counter0 Output Compare Register
|
||||
.equ OCR0_0 = 0 ;
|
||||
.equ OCR0_1 = 1 ;
|
||||
.equ OCR0_2 = 2 ;
|
||||
.equ OCR0_3 = 3 ;
|
||||
.equ OCR0_4 = 4 ;
|
||||
.equ OCR0_5 = 5 ;
|
||||
.equ OCR0_6 = 6 ;
|
||||
.equ OCR0_7 = 7 ;
|
||||
|
||||
; OCR0A - Timer/Counter0 Output Compare Register
|
||||
;.equ OCR0_0 = 0 ;
|
||||
;.equ OCR0_1 = 1 ;
|
||||
;.equ OCR0_2 = 2 ;
|
||||
;.equ OCR0_3 = 3 ;
|
||||
;.equ OCR0_4 = 4 ;
|
||||
;.equ OCR0_5 = 5 ;
|
||||
;.equ OCR0_6 = 6 ;
|
||||
;.equ OCR0_7 = 7 ;
|
||||
|
||||
; TCCR0A - Timer/Counter Control Register A
|
||||
.equ WGM00 = 0 ; Waveform Generation Mode
|
||||
.equ WGM01 = 1 ; Waveform Generation Mode
|
||||
.equ COM0B0 = 4 ; Compare Match Output B Mode
|
||||
.equ COM0B1 = 5 ; Compare Match Output B Mode
|
||||
.equ COM0A0 = 6 ; Compare Match Output A Mode
|
||||
.equ COM0A1 = 7 ; Compare Match Output A Mode
|
||||
|
||||
; TCNT0 - Timer/Counter0
|
||||
.equ TCNT0_0 = 0 ;
|
||||
.equ TCNT0_1 = 1 ;
|
||||
.equ TCNT0_2 = 2 ;
|
||||
.equ TCNT0_3 = 3 ;
|
||||
.equ TCNT0_4 = 4 ;
|
||||
.equ TCNT0_5 = 5 ;
|
||||
.equ TCNT0_6 = 6 ;
|
||||
.equ TCNT0_7 = 7 ;
|
||||
|
||||
; TCCR0B - Timer/Counter Control Register B
|
||||
.equ TCCR0 = TCCR0B ; For compatibility
|
||||
.equ CS00 = 0 ; Clock Select
|
||||
.equ CS01 = 1 ; Clock Select
|
||||
.equ CS02 = 2 ; Clock Select
|
||||
.equ WGM02 = 3 ;
|
||||
.equ FOC0B = 6 ; Force Output Compare B
|
||||
.equ FOC0A = 7 ; Force Output Compare B
|
||||
|
||||
|
||||
; ***** TIMER_COUNTER_1 **************
|
||||
; TIMSK - Timer/Counter Interrupt Mask Register
|
||||
.equ ICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable
|
||||
.equ TICIE = ICIE1 ; For compatibility
|
||||
.equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable
|
||||
.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable
|
||||
.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
; TIFR - Timer/Counter Interrupt Flag register
|
||||
.equ ICF1 = 3 ; Input Capture Flag 1
|
||||
.equ OCF1B = 5 ; Output Compare Flag 1B
|
||||
.equ OCF1A = 6 ; Output Compare Flag 1A
|
||||
.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag
|
||||
|
||||
; TCCR1A - Timer/Counter1 Control Register A
|
||||
.equ WGM10 = 0 ; Pulse Width Modulator Select Bit 0
|
||||
.equ PWM10 = WGM10 ; For compatibility
|
||||
.equ WGM11 = 1 ; Pulse Width Modulator Select Bit 1
|
||||
.equ PWM11 = WGM11 ; For compatibility
|
||||
.equ COM1B0 = 4 ; Comparet Ouput Mode 1B, bit 0
|
||||
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
|
||||
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0
|
||||
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
|
||||
|
||||
; TCCR1B - Timer/Counter1 Control Register B
|
||||
.equ CS10 = 0 ; Clock Select bit 0
|
||||
.equ CS11 = 1 ; Clock Select 1 bit 1
|
||||
.equ CS12 = 2 ; Clock Select1 bit 2
|
||||
.equ WGM12 = 3 ; Waveform Generation Mode Bit 2
|
||||
.equ CTC1 = WGM12 ; For compatibility
|
||||
.equ WGM13 = 4 ; Waveform Generation Mode Bit 3
|
||||
.equ ICES1 = 6 ; Input Capture 1 Edge Select
|
||||
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
|
||||
|
||||
; TCCR1C - Timer/Counter1 Control Register C
|
||||
.equ FOC1B = 6 ; Force Output Compare for Channel B
|
||||
.equ FOC1A = 7 ; Force Output Compare for Channel A
|
||||
|
||||
|
||||
; ***** WATCHDOG *********************
|
||||
; WDTCR - Watchdog Timer Control Register
|
||||
.equ WDTCSR = WDTCR ; For compatibility
|
||||
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
|
||||
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
|
||||
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
|
||||
.equ WDE = 3 ; Watch Dog Enable
|
||||
.equ WDCE = 4 ; Watchdog Change Enable
|
||||
.equ WDTOE = WDCE ; For compatibility
|
||||
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
|
||||
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable
|
||||
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag
|
||||
|
||||
|
||||
; ***** EXTERNAL_INTERRUPT ***********
|
||||
; GIMSK - General Interrupt Mask Register
|
||||
.equ PCIE = 5 ;
|
||||
.equ INT0 = 6 ; External Interrupt Request 0 Enable
|
||||
.equ INT1 = 7 ; External Interrupt Request 1 Enable
|
||||
|
||||
; EIFR - Extended Interrupt Flag Register
|
||||
.equ GIFR = EIFR ; For compatibility
|
||||
.equ PCIF = 5 ;
|
||||
.equ INTF0 = 6 ; External Interrupt Flag 0
|
||||
.equ INTF1 = 7 ; External Interrupt Flag 1
|
||||
|
||||
|
||||
; ***** USART ************************
|
||||
; UDR - USART I/O Data Register
|
||||
.equ UDR0 = 0 ; USART I/O Data Register bit 0
|
||||
.equ UDR1 = 1 ; USART I/O Data Register bit 1
|
||||
.equ UDR2 = 2 ; USART I/O Data Register bit 2
|
||||
.equ UDR3 = 3 ; USART I/O Data Register bit 3
|
||||
.equ UDR4 = 4 ; USART I/O Data Register bit 4
|
||||
.equ UDR5 = 5 ; USART I/O Data Register bit 5
|
||||
.equ UDR6 = 6 ; USART I/O Data Register bit 6
|
||||
.equ UDR7 = 7 ; USART I/O Data Register bit 7
|
||||
|
||||
; UCSRA - USART Control and Status Register A
|
||||
.equ USR = UCSRA ; For compatibility
|
||||
.equ MPCM = 0 ; Multi-processor Communication Mode
|
||||
.equ U2X = 1 ; Double the USART Transmission Speed
|
||||
.equ UPE = 2 ; USART Parity Error
|
||||
.equ PE = UPE ; For compatibility
|
||||
.equ DOR = 3 ; Data overRun
|
||||
.equ FE = 4 ; Framing Error
|
||||
.equ UDRE = 5 ; USART Data Register Empty
|
||||
.equ TXC = 6 ; USART Transmitt Complete
|
||||
.equ RXC = 7 ; USART Receive Complete
|
||||
|
||||
; UCSRB - USART Control and Status Register B
|
||||
.equ UCR = UCSRB ; For compatibility
|
||||
.equ TXB8 = 0 ; Transmit Data Bit 8
|
||||
.equ RXB8 = 1 ; Receive Data Bit 8
|
||||
.equ UCSZ2 = 2 ; Character Size
|
||||
.equ CHR9 = UCSZ2 ; For compatibility
|
||||
.equ TXEN = 3 ; Transmitter Enable
|
||||
.equ RXEN = 4 ; Receiver Enable
|
||||
.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable
|
||||
.equ TXCIE = 6 ; TX Complete Interrupt Enable
|
||||
.equ RXCIE = 7 ; RX Complete Interrupt Enable
|
||||
|
||||
; UCSRC - USART Control and Status Register C
|
||||
.equ UCPOL = 0 ; Clock Polarity
|
||||
.equ UCSZ0 = 1 ; Character Size Bit 0
|
||||
.equ UCSZ1 = 2 ; Character Size Bit 1
|
||||
.equ USBS = 3 ; Stop Bit Select
|
||||
.equ UPM0 = 4 ; Parity Mode Bit 0
|
||||
.equ UPM1 = 5 ; Parity Mode Bit 1
|
||||
.equ UMSEL = 6 ; USART Mode Select
|
||||
|
||||
.equ UBRR = UBRRL ; For compatibility
|
||||
|
||||
; ***** ANALOG_COMPARATOR ************
|
||||
; ACSR - Analog Comparator Control And Status Register
|
||||
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
|
||||
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
|
||||
.equ ACIC = 2 ;
|
||||
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
|
||||
.equ ACI = 4 ; Analog Comparator Interrupt Flag
|
||||
.equ ACO = 5 ; Analog Compare Output
|
||||
.equ ACBG = 6 ; Analog Comparator Bandgap Select
|
||||
.equ ACD = 7 ; Analog Comparator Disable
|
||||
|
||||
; DIDR - Digital Input Disable Register 1
|
||||
.equ AIN0D = 0 ; AIN0 Digital Input Disable
|
||||
.equ AIN1D = 1 ; AIN1 Digital Input Disable
|
||||
|
||||
|
||||
; ***** PORTD ************************
|
||||
; PORTD - Data Register, Port D
|
||||
.equ PORTD0 = 0 ;
|
||||
.equ PD0 = 0 ; For compatibility
|
||||
.equ PORTD1 = 1 ;
|
||||
.equ PD1 = 1 ; For compatibility
|
||||
.equ PORTD2 = 2 ;
|
||||
.equ PD2 = 2 ; For compatibility
|
||||
.equ PORTD3 = 3 ;
|
||||
.equ PD3 = 3 ; For compatibility
|
||||
.equ PORTD4 = 4 ;
|
||||
.equ PD4 = 4 ; For compatibility
|
||||
.equ PORTD5 = 5 ;
|
||||
.equ PD5 = 5 ; For compatibility
|
||||
.equ PORTD6 = 6 ;
|
||||
.equ PD6 = 6 ; For compatibility
|
||||
|
||||
; DDRD
|
||||
.equ DDD0 = 0 ;
|
||||
.equ DDD1 = 1 ;
|
||||
.equ DDD2 = 2 ;
|
||||
.equ DDD3 = 3 ;
|
||||
.equ DDD4 = 4 ;
|
||||
.equ DDD5 = 5 ;
|
||||
.equ DDD6 = 6 ;
|
||||
|
||||
; PIND - Input Pins, Port D
|
||||
.equ PIND0 = 0 ;
|
||||
.equ PIND1 = 1 ;
|
||||
.equ PIND2 = 2 ;
|
||||
.equ PIND3 = 3 ;
|
||||
.equ PIND4 = 4 ;
|
||||
.equ PIND5 = 5 ;
|
||||
.equ PIND6 = 6 ;
|
||||
|
||||
|
||||
; ***** EEPROM ***********************
|
||||
; EEAR - EEPROM Read/Write Access
|
||||
.equ EEARL = EEAR ; For compatibility
|
||||
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0
|
||||
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1
|
||||
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2
|
||||
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3
|
||||
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4
|
||||
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5
|
||||
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6
|
||||
|
||||
; EEDR - EEPROM Data Register
|
||||
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
|
||||
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
|
||||
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
|
||||
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
|
||||
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
|
||||
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
|
||||
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
|
||||
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
|
||||
|
||||
; EECR - EEPROM Control Register
|
||||
.equ EERE = 0 ; EEPROM Read Enable
|
||||
.equ EEPE = 1 ; EEPROM Write Enable
|
||||
.equ EEWE = EEPE ; For compatibility
|
||||
.equ EEMPE = 2 ; EEPROM Master Write Enable
|
||||
.equ EEMWE = EEMPE ; For compatibility
|
||||
.equ EERIE = 3 ; EEProm Ready Interrupt Enable
|
||||
.equ EEPM0 = 4 ;
|
||||
.equ EEPM1 = 5 ;
|
||||
|
||||
|
||||
; ***** PORTA ************************
|
||||
; PORTA - Port A Data Register
|
||||
.equ PORTA0 = 0 ; Port A Data Register bit 0
|
||||
.equ PA0 = 0 ; For compatibility
|
||||
.equ PORTA1 = 1 ; Port A Data Register bit 1
|
||||
.equ PA1 = 1 ; For compatibility
|
||||
.equ PORTA2 = 2 ; Port A Data Register bit 2
|
||||
.equ PA2 = 2 ; For compatibility
|
||||
|
||||
; DDRA - Port A Data Direction Register
|
||||
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
|
||||
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
|
||||
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
|
||||
|
||||
; PINA - Port A Input Pins
|
||||
.equ PINA0 = 0 ; Input Pins, Port A bit 0
|
||||
.equ PINA1 = 1 ; Input Pins, Port A bit 1
|
||||
.equ PINA2 = 2 ; Input Pins, Port A bit 2
|
||||
|
||||
|
||||
; ***** CPU **************************
|
||||
; SREG - Status Register
|
||||
.equ SREG_C = 0 ; Carry Flag
|
||||
.equ SREG_Z = 1 ; Zero Flag
|
||||
.equ SREG_N = 2 ; Negative Flag
|
||||
.equ SREG_V = 3 ; Two's Complement Overflow Flag
|
||||
.equ SREG_S = 4 ; Sign Bit
|
||||
.equ SREG_H = 5 ; Half Carry Flag
|
||||
.equ SREG_T = 6 ; Bit Copy Storage
|
||||
.equ SREG_I = 7 ; Global Interrupt Enable
|
||||
|
||||
; SPMCSR - Store Program Memory Control and Status register
|
||||
.equ SPMEN = 0 ; Store Program Memory Enable
|
||||
.equ PGERS = 1 ; Page Erase
|
||||
.equ PGWRT = 2 ; Page Write
|
||||
.equ RFLB = 3 ; Read Fuse and Lock Bits
|
||||
.equ CTPB = 4
|
||||
|
||||
; MCUCR - MCU Control Register
|
||||
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
|
||||
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
|
||||
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0
|
||||
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1
|
||||
.equ SM0 = 4 ; Sleep Mode Select Bit 0
|
||||
.equ SM = SM0 ; For compatibility
|
||||
.equ SE = 5 ; Sleep Enable
|
||||
.equ SM1 = 6 ; Sleep Mode Select Bit 1
|
||||
.equ PUD = 7 ; Pull-up Disable
|
||||
|
||||
; CLKPR - Clock Prescale Register
|
||||
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0
|
||||
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1
|
||||
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2
|
||||
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3
|
||||
.equ CLKPCE = 7 ; Clock Prescaler Change Enable
|
||||
|
||||
; MCUSR - MCU Status register
|
||||
.equ PORF = 0 ; Power-On Reset Flag
|
||||
.equ EXTRF = 1 ; External Reset Flag
|
||||
.equ BORF = 2 ; Brown-out Reset Flag
|
||||
.equ WDRF = 3 ; Watchdog Reset Flag
|
||||
|
||||
; OSCCAL - Oscillator Calibration Register
|
||||
.equ CAL0 = 0 ; Oscillatro Calibration Value Bit 0
|
||||
.equ CAL1 = 1 ; Oscillatro Calibration Value Bit 1
|
||||
.equ CAL2 = 2 ; Oscillatro Calibration Value Bit 2
|
||||
.equ CAL3 = 3 ; Oscillatro Calibration Value Bit 3
|
||||
.equ CAL4 = 4 ; Oscillatro Calibration Value Bit 4
|
||||
.equ CAL5 = 5 ; Oscillatro Calibration Value Bit 5
|
||||
.equ CAL6 = 6 ; Oscillatro Calibration Value Bit 6
|
||||
|
||||
; GTCCR - General Timer Counter Control Register
|
||||
.equ SFIOR = GTCCR ; For compatibility
|
||||
.equ PSR10 = 0 ;
|
||||
|
||||
; PCMSK - Pin-Change Mask register
|
||||
.equ PCINT0 = 0 ; Pin-Change Interrupt 0
|
||||
.equ PCINT1 = 1 ; Pin-Change Interrupt 1
|
||||
.equ PCINT2 = 2 ; Pin-Change Interrupt 2
|
||||
.equ PCINT3 = 3 ; Pin-Change Interrupt 3
|
||||
.equ PCINT4 = 4 ; Pin-Change Interrupt 4
|
||||
.equ PCINT5 = 5 ; Pin-Change Interrupt 5
|
||||
.equ PCINT6 = 6 ; Pin-Change Interrupt 6
|
||||
.equ PCINT7 = 7 ; Pin-Change Interrupt 7
|
||||
|
||||
; GPIOR2 - General Purpose I/O Register 2
|
||||
.equ GPIOR20 = 0 ; General Purpose I/O Register 2 bit 0
|
||||
.equ GPIOR21 = 1 ; General Purpose I/O Register 2 bit 1
|
||||
.equ GPIOR22 = 2 ; General Purpose I/O Register 2 bit 2
|
||||
.equ GPIOR23 = 3 ; General Purpose I/O Register 2 bit 3
|
||||
.equ GPIOR24 = 4 ; General Purpose I/O Register 2 bit 4
|
||||
.equ GPIOR25 = 5 ; General Purpose I/O Register 2 bit 5
|
||||
.equ GPIOR26 = 6 ; General Purpose I/O Register 2 bit 6
|
||||
.equ GPIOR27 = 7 ; General Purpose I/O Register 2 bit 7
|
||||
|
||||
; GPIOR1 - General Purpose I/O Register 1
|
||||
.equ GPIOR10 = 0 ; General Purpose I/O Register 1 bit 0
|
||||
.equ GPIOR11 = 1 ; General Purpose I/O Register 1 bit 1
|
||||
.equ GPIOR12 = 2 ; General Purpose I/O Register 1 bit 2
|
||||
.equ GPIOR13 = 3 ; General Purpose I/O Register 1 bit 3
|
||||
.equ GPIOR14 = 4 ; General Purpose I/O Register 1 bit 4
|
||||
.equ GPIOR15 = 5 ; General Purpose I/O Register 1 bit 5
|
||||
.equ GPIOR16 = 6 ; General Purpose I/O Register 1 bit 6
|
||||
.equ GPIOR17 = 7 ; General Purpose I/O Register 1 bit 7
|
||||
|
||||
; GPIOR0 - General Purpose I/O Register 0
|
||||
.equ GPIOR00 = 0 ; General Purpose I/O Register 0 bit 0
|
||||
.equ GPIOR01 = 1 ; General Purpose I/O Register 0 bit 1
|
||||
.equ GPIOR02 = 2 ; General Purpose I/O Register 0 bit 2
|
||||
.equ GPIOR03 = 3 ; General Purpose I/O Register 0 bit 3
|
||||
.equ GPIOR04 = 4 ; General Purpose I/O Register 0 bit 4
|
||||
.equ GPIOR05 = 5 ; General Purpose I/O Register 0 bit 5
|
||||
.equ GPIOR06 = 6 ; General Purpose I/O Register 0 bit 6
|
||||
.equ GPIOR07 = 7 ; General Purpose I/O Register 0 bit 7
|
||||
|
||||
|
||||
; ***** USI **************************
|
||||
; USIDR - USI Data Register
|
||||
.equ USIDR0 = 0 ; USI Data Register bit 0
|
||||
.equ USIDR1 = 1 ; USI Data Register bit 1
|
||||
.equ USIDR2 = 2 ; USI Data Register bit 2
|
||||
.equ USIDR3 = 3 ; USI Data Register bit 3
|
||||
.equ USIDR4 = 4 ; USI Data Register bit 4
|
||||
.equ USIDR5 = 5 ; USI Data Register bit 5
|
||||
.equ USIDR6 = 6 ; USI Data Register bit 6
|
||||
.equ USIDR7 = 7 ; USI Data Register bit 7
|
||||
|
||||
; USISR - USI Status Register
|
||||
.equ USICNT0 = 0 ; USI Counter Value Bit 0
|
||||
.equ USICNT1 = 1 ; USI Counter Value Bit 1
|
||||
.equ USICNT2 = 2 ; USI Counter Value Bit 2
|
||||
.equ USICNT3 = 3 ; USI Counter Value Bit 3
|
||||
.equ USIDC = 4 ; Data Output Collision
|
||||
.equ USIPF = 5 ; Stop Condition Flag
|
||||
.equ USIOIF = 6 ; Counter Overflow Interrupt Flag
|
||||
.equ USISIF = 7 ; Start Condition Interrupt Flag
|
||||
|
||||
; USICR - USI Control Register
|
||||
.equ USITC = 0 ; Toggle Clock Port Pin
|
||||
.equ USICLK = 1 ; Clock Strobe
|
||||
.equ USICS0 = 2 ; USI Clock Source Select Bit 0
|
||||
.equ USICS1 = 3 ; USI Clock Source Select Bit 1
|
||||
.equ USIWM0 = 4 ; USI Wire Mode Bit 0
|
||||
.equ USIWM1 = 5 ; USI Wire Mode Bit 1
|
||||
.equ USIOIE = 6 ; Counter Overflow Interrupt Enable
|
||||
.equ USISIE = 7 ; Start Condition Interrupt Enable
|
||||
|
||||
|
||||
|
||||
; ***** LOCKSBITS ********************************************************
|
||||
.equ LB1 = 0 ; Lockbit
|
||||
.equ LB2 = 1 ; Lockbit
|
||||
|
||||
|
||||
; ***** FUSES ************************************************************
|
||||
; LOW fuse bits
|
||||
.equ CKSEL0 = 0 ; Select Clock Source
|
||||
.equ CKSEL1 = 1 ; Select Clock Source
|
||||
.equ CKSEL2 = 2 ; Select Clock Source
|
||||
.equ CKSEL3 = 3 ; Select Clock Source
|
||||
.equ SUT0 = 4 ; Select start-up time
|
||||
.equ SUT1 = 5 ; Select start-up time
|
||||
.equ CKOUT = 6 ; Clock output
|
||||
.equ CKDIV8 = 7 ; Divide clock by 8
|
||||
|
||||
; HIGH fuse bits
|
||||
.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level
|
||||
.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level
|
||||
.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level
|
||||
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
|
||||
.equ WDTON = 4 ; Watchdog Timer Always On
|
||||
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
|
||||
.equ DWEN = 6 ; debugWIRE Enable
|
||||
.equ RSTDISBL = 7 ; External reset disable
|
||||
|
||||
; EXTENDED fuse bits
|
||||
.equ SELFPRGEN = 0 ; Self Programming Enable
|
||||
|
||||
|
||||
|
||||
; ***** CPU REGISTER DEFINITIONS *****************************************
|
||||
.def XH = r27
|
||||
.def XL = r26
|
||||
.def YH = r29
|
||||
.def YL = r28
|
||||
.def ZH = r31
|
||||
.def ZL = r30
|
||||
|
||||
|
||||
|
||||
; ***** DATA MEMORY DECLARATIONS *****************************************
|
||||
.equ FLASHEND = 0x03ff ; Note: Word address
|
||||
.equ IOEND = 0x003f
|
||||
.equ SRAM_START = 0x0060
|
||||
.equ SRAM_SIZE = 128
|
||||
.equ RAMEND = 0x00df
|
||||
.equ XRAMEND = 0x0000
|
||||
.equ E2END = 0x007f
|
||||
.equ EEPROMEND = 0x007f
|
||||
.equ EEADRBITS = 7
|
||||
#pragma AVRPART MEMORY PROG_FLASH 2048
|
||||
#pragma AVRPART MEMORY EEPROM 128
|
||||
#pragma AVRPART MEMORY INT_SRAM SIZE 128
|
||||
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
|
||||
|
||||
|
||||
|
||||
; ***** BOOTLOADER DECLARATIONS ******************************************
|
||||
.equ NRWW_START_ADDR = 0x0
|
||||
.equ NRWW_STOP_ADDR = 0x3ff
|
||||
.equ RWW_START_ADDR = 0x0
|
||||
.equ RWW_STOP_ADDR = 0x0
|
||||
.equ PAGESIZE = 16
|
||||
|
||||
|
||||
|
||||
; ***** INTERRUPT VECTORS ************************************************
|
||||
.equ INT0addr = 0x0001 ; External Interrupt Request 0
|
||||
.equ INT1addr = 0x0002 ; External Interrupt Request 1
|
||||
.equ ICP1addr = 0x0003 ; Timer/Counter1 Capture Event
|
||||
.equ OC1Aaddr = 0x0004 ; Timer/Counter1 Compare Match A
|
||||
.equ OC1addr = 0x0004 ; For compatibility
|
||||
.equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow
|
||||
.equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow
|
||||
.equ URXCaddr = 0x0007 ; USART, Rx Complete
|
||||
.equ URXC0addr = 0x0007 ; For compatibility
|
||||
.equ UDREaddr = 0x0008 ; USART Data Register Empty
|
||||
.equ UDRE0addr = 0x0008 ; For compatibility
|
||||
.equ UTXCaddr = 0x0009 ; USART, Tx Complete
|
||||
.equ UTXC0addr = 0x0009 ; For compatibility
|
||||
.equ ACIaddr = 0x000a ; Analog Comparator
|
||||
.equ PCIaddr = 0x000b ;
|
||||
.equ OC1Baddr = 0x000c ;
|
||||
.equ OC0Aaddr = 0x000d ;
|
||||
.equ OC0Baddr = 0x000e ;
|
||||
.equ USI_STARTaddr = 0x000f ; USI Start Condition
|
||||
.equ USI_OVFaddr = 0x0010 ; USI Overflow
|
||||
.equ ERDYaddr = 0x0011 ;
|
||||
.equ WDTaddr = 0x0012 ; Watchdog Timer Overflow
|
||||
|
||||
.equ INT_VECTORS_SIZE = 19 ; size in words
|
||||
|
||||
#endif /* _TN2313DEF_INC_ */
|
||||
|
||||
; ***** END OF FILE ******************************************************
|
||||
BIN
PPMDecoder/PPMDecoder.epb
Executable file
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PPMDecoder/PPMDecoder.epb
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PPMDecoder/RCRXDecoder.vsd
Executable file
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PPMDecoder/RCRXDecoder.vsd
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PPMDecoder/WingmanRCRXDecoder_Layout.pdf
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PPMDecoder/WingmanRCRXDecoder_Layout.pdf
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PPMDecoder/WingmanRCRXDecoder_Schematic.pdf
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PPMDecoder/WingmanRCRXDecoder_Schematic.pdf
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PPMDecoder/WingmanRCRXDecoder_Screen.pdf
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PPMDecoder/WingmanRCRXDecoder_Screen.pdf
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PPMEncoder/PPMEncoder.epb
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PPMEncoder/PPMEncoder.epb
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PPMEncoder/WingmanRCTXEncoder_Schematic.pdf
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PPMEncoder/WingmanRCTXEncoder_Schematic.pdf
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SecMotorDriver/SecMotorDriver.epb
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SecMotorDriver/SecMotorDriver.epb
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SecMotorDriver/WingmanSecMotorDriver_Layout.pdf
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SecMotorDriver/WingmanSecMotorDriver_Layout.pdf
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SecMotorDriver/WingmanSecMotorDriver_Schematic.pdf
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SecMotorDriver/WingmanSecMotorDriver_Schematic.pdf
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SecMotorDriver/WingmanSecMotorDriver_Screen.pdf
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SecMotorDriver/WingmanSecMotorDriver_Screen.pdf
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Wingman Elektronik.doc
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Wingman Elektronik.doc
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Wingman-elektronik.vsd
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Wingman-elektronik.vsd
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Wingman_Slutrapport.pdf
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Wingman_Slutrapport.pdf
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fartreglage.vsd
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fartreglage.vsd
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metod1.epb
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metod1.epb
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metod2.epb
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metod2.epb
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metod4.epb
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metod4.epb
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Reference in New Issue
Block a user