302 lines
15 KiB
C
302 lines
15 KiB
C
#ifndef CC1100_H
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#define CC1100_H
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/*================================================================================================
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cc1100.h SiWiCom copyright 2006 v1.0 (2006-05-11)
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Name: Joakim Nilsson E-mail: mail@jopin.se
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Name: Christoffer Martinsson E-mail: cm@cmtec.se
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Description: Routines for cc1100. Uses usart.h as tranceiver
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Hardware configuration is done by hardware.h witch must contain definitions for:
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(X=letter i.e PORTX=PORTB, n=number i.e PXn=PB4)
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GDO0 PXn (Example: #define GDO0 PC1)
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GDO0_PORT PORTX (Example: #define GDO0_PORT PORTC)
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GDO0_DDR DDRX (Example: #define GDO0_DDR DDRC)
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GDO0_PIN PINX (Example: #define GDO0_PIN PINC)
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GDO2 PXn (Example: #define GDO2 PD3)
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GDO2_PORT PORTX (Example: #define GDO2_PORT PORTD)
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GDO2_DDR DDRX (Example: #define GDO2_DDR DDRD)
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GDO2_PIN PINX (Example: #define GDO2_PIN PIND)
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CS_CC1100 SPI_CSX_NR (Example: #define CS_CC1100 SPI_CS0_NR)
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================================================================================================*/
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/*================================================================================================
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Definition of configuration registers for CC1100
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================================================================================================*/
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#define IOCFG2 0x00 // GDO2 output pin configuration s45
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#define IOCFG1 0x01 // GDO1 output pin configuration s45
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#define IOCFG0D 0x02 // GDO0 output pin configuration s45
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#define FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds s46
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#define SYNC1 0x04 // Sync word, high byte s46
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#define SYNC0 0x05 // Sync word, low byte s46
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#define PKTLEN 0x06 // Packet length Yes s46
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#define PKTCTRL1 0x07 // Packet automation control s47
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#define PKTCTRL0 0x08 // Packet automation control s48
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#define ADDR 0x09 // Device address s48
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#define CHANNR 0x0A // Channel number s48
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#define FSCTRL1 0x0B // Frequency synthesizer control s49
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#define FSCTRL0 0x0C // Frequency synthesizer control s49
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#define FREQ2 0x0D // Frequency control word, high byte s49
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#define FREQ1 0x0E // Frequency control word, middle byte s50
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#define FREQ0 0x0F // Frequency control word, low byte s50
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#define MDMCFG4 0x10 // Modem configuration s50
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#define MDMCFG3 0x11 // Modem configuration s50
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#define MDMCFG2 0x12 // Modem configuration s51
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#define MDMCFG1 0x13 // Modem configuration s52
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#define MDMCFG0 0x14 // Modem configuration s52
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#define DEVIATN 0x15 // Modem deviation setting s52
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#define MCSM2 0x16 // Main Radio Control State Machine configuration s53
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#define MCSM1 0x17 // Main Radio Control State Machine configuration s54
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#define MCSM0 0x18 // Main Radio Control State Machine configuration s55
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#define FOCCFG 0x19 // Frequency Offset Compensation configuration s55
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#define BSCFG 0x1A // Bit Synchronization configuration s55
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#define AGCCTRL2 0x1B // AGC control s55
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#define AGCCTRL1 0x1C // AGC control s56
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#define AGCCTRL0 0x1D // AGC control s56
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#define WOREVT1 0x1E // High byte Event 0 timeout s56
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#define WOREVT0 0x1F // Low byte Event 0 timeout s56
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#define WORCTRL 0x20 // Wake On Radio control s57
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#define FREND1 0x21 // Front end RX configuration s57
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#define FREND0 0x22 // Front end TX configuration s58
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#define FSCAL3 0x23 // Frequency synthesizer calibration s58
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#define FSCAL2 0x24 // Frequency synthesizer calibration s58
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#define FSCAL1 0x25 // Frequency synthesizer calibration s58
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#define FSCAL0 0x26 // Frequency synthesizer calibration s59
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#define RCCTRL1 0x27 // RC oscillator configuration s59
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#define RCCTRL0 0x28 // RC oscillator configuration s59
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#define FSTEST 0x29 // Frequency synthesizer calibration control s59
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#define PTEST 0x2A // Production test s59
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#define AGCTEST 0x2B // AGC test s59
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#define TEST2 0x2C // Various test settings s60
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#define TEST1 0x2D // Various test settings s60
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#define TEST0 0x2E // Various test settings s60
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/*================================================================================================
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Definition of status registers for CC1100. Vad betyder adressen inom parates?? (Fr<46>n manualen s43)
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================================================================================================*/
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#define PARTNUM 0x30 // (0xF0) Part number for CC1100 s60
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#define VERSION 0x31 // (0xF1) Current version number s60
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#define FREQEST 0x32 // (0xF2) Frequency Offset Estimate s60
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#define LQI 0x33 // (0xF3) Demodulator estimate for Link Quality s60
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#define RSSI 0x34 // (0xF4) Received signal strength indication s61
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#define MARCSTATE 0x35 // (0xF5) Control state machine state s61
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#define WORTIME1 0x36 // (0xF6) High byte of WOR timer s61
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#define WORTIME0 0x37 // (0xF7) Low byte of WOR timer s62
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#define PKTSTATUS 0x38 // (0xF8) Current GDOx status and packet status s62
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#define VCO_VC_DAC 0x39 // (0xF9) Current setting from PLL calibration module s62
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#define TXBYTES 0x3A // (0xFA) Underflow and number of bytes in the TX FIFO s62
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#define RXBYTES 0x3B // (0xFB) Overflow and number of bytes in the RX FIFO s62
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/*================================================================================================
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Definition of command strobes for CC1100. s41
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================================================================================================*/
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#define SRES 0x30 // Reset chip.
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#define SFSTXON 0x31 /* Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). If in RX (with CCA):
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Go to a wait state where only the synthesizer is running (for quick RX / TX turnaround).*/
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#define SXOFF 0x32 //Turn off crystal oscillator.
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#define SCAL 0x33 /* Calibrate frequency synthesizer and turn it off (enables quick start). SCAL can be strobed from
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IDLE mode without setting manual calibration mode (MCSM0.FS_AUTOCAL=0)*/
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#define SRX 0x34 // Enable RX. Perform calibration first if coming from IDLE and MCSM0.FS_AUTOCAL=1.
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#define STX 0x35 /* In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1.
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If in RX state and CCA is enabled: Only go to TX if channel is clear.*/
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#define SIDLE 0x36 // Exit RX / TX, turn off frequency synthesizer and exit Wake-On-Radio mode if applicable.
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#define SAFC 0x37 // Perform AFC adjustment of the frequency synthesizer as outlined in section 22.1.
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#define SWOR 0x38 // Start automatic RX polling sequence (Wake-on-Radio) as described in section 27.5.
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#define SPWD 0x39 // Enter power down mode when CSn goes high.
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#define SFRX 0x3A // Flush the RX FIFO buffer.
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#define SFTX 0x3B // Flush the TX FIFO buffer.
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#define SWORRST 0x3C // Reset real time clock.
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#define SNOP 0x3D // No operation. May be used to pad strobe commands to two bytes for simpler software.
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/*================================================================================================
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Definitions for GDO0,1,2 assignments CC1100. s39
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================================================================================================*/
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#define RX_FIFO_ABV_THR 0x00 /*Associated to the RX FIFO: Asserts when RX FIFO is filled above RXFIFO_THR. De-asserts
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when RX FIFO is drained below RXFIFO_THR.*/
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#define RX_FIFO_ABV_THR_END 0x01 /*Associated to the RX FIFO: Asserts when RX FIFO is filled above RXFIFO_THR or the
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end of packet is reached. Deasserts when RX FIFO is empty.*/
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#define TX_FIFO_ABV_THR 0x02 /*Associated to the TX FIFO: Asserts when the TX FIFO is filled above TXFIFO_THR.
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De-asserts when the TX FIFO is below TXFIFO_THR.*/
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#define TX_FIFO_FULL 0x03 /*Associated to the TX FIFO: Asserts when TX FIFO is full. De-asserts when the TX FIFO is drained below
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TXFIFO_THR.*/
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#define TX_FIFO_OVERFLOW 0x04 // Asserts when the RX FIFO has overflowed. De-asserts when the FIFO has been flushed.
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#define TX_FIFO_UNDERFLOW 0x05 //Asserts when the TX FIFO has underflowed. De-asserts when the FIFO is flushed.
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#define SYNKWORD_RX_TX 0x06 /*Asserts when sync word has been sent / received, and de-asserts at the end of the
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packet. In RX, the pin will de-assert when the optional address check fails or the
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RX FIFO overflows. In TX the pin will de-assert if the TX FIFO underflows.*/
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#define OK_CRC 0x07 /*Asserts when a packet has been received with OK CRC. De-asserts when the first
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byte is read from the RX FIFO.*/
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#define PQI_ABOVE_PQT 0x08 //Preamble Quality Reached. Asserts when the PQI is above the programmed PQT value.
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#define CCA 0x09 /*Clear channel assessment. High when RSSI level is below threshold (dependent
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on the current CCA_MODE setting)*/
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#define LDO 0x0A //Lock detector output
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#define SERIAL_CLK 0x0B /*Serial Clock. Synchronous to the data in synchronous serial mode. Data is set up
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on the falling edge and is read on the rising edge of SERIAL_CLK.*/
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#define SSDO 0x0C /*Serial Synchronous Data Output. Used for synchronous serial mode. The MCU must read DO on the rising edge of
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SERIAL_CLK. Data is set up on the falling edge by CC1100.*/
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#define STDO 0x0D //Serial transparent Data Output. Used for asynchronous serial mode.
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#define CARRIER_SENSE 0x0E //Carrier sense. High if RSSI level is above threshold.
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#define CRC_OK 0x0F //CRC OK. The last CRC comparison matched. Cleared when entering/restarting RX mode.
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#define RX_HD1 0x16 /*RX_HARD_DATA[1]. Can be used together with RX_SYMBOL_TICK for alternative serial
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RX output.*/
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#define RX_HD0 0x17 /*RX_HARD_DATA[0]. Can be used together with RX_SYMBOL_TICK for alternative serial
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RX output.*/
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#define PA_PD 0x1B /*PA is enabled when 1, in power-down when 0. Can be used to control external PA or
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RX/TX switch.*/
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#define LNA_PD 0x1C /*LNA is enabled when 1, in power-down when 0. Can be used to control external LNA or
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RX/TX switch.*/
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#define RX_SYMBOL_TICK 0x1D //Can be used together with RX_HARD_DATA for alternative serial RX output.
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#define CHIP_RDY 0x29 //Chip ready
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#define XOSC_STABLE 0x2B //Oscillator stable
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#define GDO0_Z_EN_N 0x2D //When this output is 0, GDO0 is configured as input (for serial TX data).
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#define THREE_STATE 0x2E //High impedance (3-state)
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#define HW_0 0x2F //HW to 0 (HW1 achieved with _INV signal)
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#define CLK_XOSC_1 0x30 //Clocksignal out on GDO-pin<69>s with optional prescaler
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#define CLK_XOSC_1_5 0x31
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#define CLK_XOSC_2 0x32
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#define CLK_XOSC_3 0x33
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#define CLK_XOSC_4 0x34
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#define CLK_XOSC_6 0x35
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#define CLK_XOSC_8 0x36
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#define CLK_XOSC_12 0x37
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#define CLK_XOSC_16 0x38
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#define CLK_XOSC_24 0x39
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#define CLK_XOSC_32 0x3A
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#define CLK_XOSC_48 0x3B
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#define CLK_XOSC_64 0x3C
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#define CLK_XOSC_96 0x3D
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#define CLK_XOSC_128 0x3E
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#define CLK_XOSC_192 0x3F
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/*================================================================================================
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================================================================================================*/
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#define READ 0x01
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#define WRITE 0x00
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#define NOBURST 0x00
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#define BURST 0x01
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/*================================================================================================
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Definition of multibyte registers
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================================================================================================*/
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#define PATABLE 0x3E
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#define TXFIFO 0x3F
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#define RXFIFO 0x3F
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/*================================================================================================
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Functions
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================================================================================================*/
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/*================================================================================================
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cc1100Select
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Description: Select cc1100 as slave
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Input: -
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Output: -
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------------------------------------------------------------------------------------------------*/
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void cc1100Select(void);
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/*===============================================================================================
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cc1100DeSelect
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Description: DeSelect cc1100
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Input: -
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Output: -
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------------------------------------------------------------------------------------------------*/
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void cc1100DeSelect(void);
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/*================================================================================================
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cc1100WriteBurstReg
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Description: Write to cc1100 registers in burst mode.
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Input: startAddr (Address to start writing)
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*regValueBuffer (data buffer contaning all data that should be written to cc1100)
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bufferSize (size of de data buffer)
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Output: -
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------------------------------------------------------------------------------------------------*/
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void cc1100WriteBurstReg(uint8_t startAddr, uint8_t *regValueBuffer, uint8_t bufferSize);
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/*================================================================================================
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cc1100ReadBurstReg
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Description: read from cc1100 registers in burst mode.
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Input: startAddr (Address to start reading)
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*regValueBuffer (data buffer for storing all data read from the cc1100)
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bufferSize (size of de data buffer)
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Output: -
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------------------------------------------------------------------------------------------------*/
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void cc1100ReadBurstReg(uint8_t startAddr, uint8_t *regValueBuffer, uint8_t bufferSize);
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/*================================================================================================
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cc1100WriteReg
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Description: Write to a cc1100 register.
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Input: regAddr (register address)
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regValue (new rigiter value)
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Output: -
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------------------------------------------------------------------------------------------------*/
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void cc1100WriteReg(uint8_t regAddr, uint8_t regValue);
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/*================================================================================================
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cc1100ReadReg
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Description: Read from a cc1100 register.
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Input: regAddr (register address)
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Output: regiter value
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------------------------------------------------------------------------------------------------*/
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uint8_t cc1100ReadReg(uint8_t regAddr);
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/*===============================================================================================
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cc1100WriteCommand
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Description: Write a command to cc1100.
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Input: cmdAddr (command register address, in the range 0x30 - 0x3D)
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Output: -
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------------------------------------------------------------------------------------------------*/
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void cc1100WriteCommand(uint8_t cmdAddr);
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/*================================================================================================
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cc1100ReadStatusReg
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Description: Read status register from cc1100
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Input: regAddr (register address)
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Output: regiter value
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------------------------------------------------------------------------------------------------*/
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uint8_t cc1100ReadStatusReg(uint8_t regAddr);
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/*=================================================================================================
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END
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=================================================================================================*/
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#endif //CC1100
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