Updated file scrtucture. Updated layout for 52 key version
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@@ -1,5 +1,6 @@
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{
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"board": {
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"3dviewports": [],
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.049999999999999996,
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@@ -131,7 +132,15 @@
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"zones_allow_external_fillets": false,
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"zones_use_no_outline": true
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},
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"layer_presets": []
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"ipc2581": {
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"dist": "",
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"distpn": "",
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"internal_id": "",
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"mfg": "",
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"mpn": ""
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},
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"layer_presets": [],
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"viewports": []
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},
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"boards": [],
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"cvpcb": {
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@@ -353,7 +362,7 @@
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"net_settings": {
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"classes": [
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{
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"bus_width": 12.0,
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"bus_width": 12,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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@@ -367,10 +376,10 @@
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"track_width": 0.25,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"wire_width": 6.0
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"wire_width": 6
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},
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{
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"bus_width": 12.0,
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"bus_width": 12,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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@@ -379,29 +388,36 @@
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "Power",
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"nets": [
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"+5V"
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],
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.5,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"wire_width": 6.0
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"wire_width": 6
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}
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],
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"meta": {
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"version": 2
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"version": 3
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},
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"net_colors": null
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"net_colors": null,
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"netclass_assignments": null,
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"netclass_patterns": [
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{
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"netclass": "Power",
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"pattern": "+5V"
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}
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]
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},
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"pcbnew": {
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"last_paths": {
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"gencad": "",
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"idf": "",
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"netlist": "",
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"plot": "",
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"pos_files": "",
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"specctra_dsn": "",
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"step": "../../mechanics/cmdr_mainboard.step",
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"svg": "",
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"vrml": ""
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},
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"page_layout_descr_file": ""
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